Taiwan Semiconductor Manufacturing Comp. Ltd.

National Taiwan University

TSMC Solid State Lighting Ltd.

Chao-Hsiung Wang

Chi-Wen Liu

Kuo-Cheng Ching

Denny Tang

Chenming Hu

Chien-Chao Huang

Wen-Chin Lin

Fu-Liang Yang

Li-Shyue Lai

Horng-Huei Tseng

Yee-Chia Yeo

Guan-Lin Chen

Chun-Hsiung Tsai

Zi-Wei Fang

Ping-Kun Wu

Jiun-Jia Huang

Kuo-Cheng Lee

Yun-Wei Cheng

Chun-Hao Chou

Yung-Lung Hsu

Tsung-Han Tsai

Hung-Wei Chen

Harry-Hak-Lay Chuang

Ming Zhu

Chun-Chieh Lin

Yi-Ren Chen

Kuo-Cheng Chiang

Tzu-Hsuan Hsu

Hsin-Chieh Huang

Samuel C Pan

Jenn-Gwo Hwu

Ting-Hung Hsu

Sheng-Da Liu

Wei-Cheng Tian

Shih-Chang Chen

Mong-Song Liang

Chang-Yun Chang

Liang-Gi Yao

Tang-Xuan Zhong

Tien-Chih Chang

Horng Huei Tseng

Jiun-Lei Jerry Yu

Wen-Chin Lee

Hsin-Hui Lee

Ming-Cheng Lin

Yu-Syuan Lin

Chung-Hu Ge

Wen Chin Lin

Chun Chich Lin

Chen-Hua Douglas Yu

Shau-Lin Shue

Chin-Hsiang Lin

Cheng-Yuan Tsai

Yu-Jen Wang

Zhiqiang Wu

Heng-Hsin Liu

Zhi-Chang Lin

Wai-Yi Lien

Hao-Yu Chen

Jui-Chun Peng

Yi-Lung Cheng

Chih-Huang Lai

Fang-Shi Jordan Lai

Hung-Chih Chen

Denny Duan-Lee Tang

Tai-Bor Wu

Wei-Hsiang Tseng

Chen Ming Hu

Ho-Ping Chen

Hsien-Wei Chin

Chun Chieh Lin

Ding-Chung Lu

Wen-Chen Lin

Mark Hsieh

Fan-Shi Jordan Lai

Chine-Gie Lo

Hway Chi Lin

Yuan-Chieh Tseng

Niahn-Mauh Shih

Tang-Xuang Zhong

Chang-Yu Chang

A device includes a substrate including a low-resistance top surface and a fin structure including a first fin and a second fin. Each of the first and second fins includes a low-resistance fin-top surface and two low-resistance sidewall surfaces. The device includes an insulation material over the top surface of the substrate and between the first fin and the second fin. The fin-top surface and a first portion of the sidewall surfaces of each of the first and the second fins are above the insulation material. The device further includes a dielectric layer over the insulation material and in direct contact with the fin-top surface and the first portion of the sidewall surfaces of each of the first and the second fins; a first electrode in direct contact with the fin-top surface of the first fin; and a second electrode over the dielectric layer that is over the second fin.

3D capacitor and method of manufacturing same

Systems and methods are provided for fabricating semiconductor device structures on a substrate. A first fin structure is formed on a substrate. A second fin structure is formed on the substrate. A first semiconductor material is formed on both the first fin structure and the second fin structure. A second semiconductor material is formed on the first semiconductor material on both the first fin structure and the second fin structure. The first semiconductor material on the first fin structure is oxidized to form a first oxide. The second semiconductor material on the first fin structure is removed. A first dielectric material and a first electrode are formed on the first fin structure. A second dielectric material and a second electrode are formed on the second fin structure.

Systems and methods for fabricating FinFETs with different threshold voltages

The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.

Structure and method for vertical tunneling field effect transistor with leveled source and drain

A back side illumination (BSI) image sensor with a dielectric grid opening having a planar lower surface is provided. A pixel sensor is arranged within a semiconductor substrate. A metallic grid is arranged over the pixel sensor and defines a sidewall of a metallic grid opening. A dielectric grid is arranged over the metallic grid and defines a sidewall of the dielectric grid opening. A capping layer is arranged over the metallic grid, and defines the planar lower surface of the dielectric grid opening.

Stacked grid design for improved optical performance and isolation

A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

Semiconductor device having semiconductor alloy layer adjacent a gate structure

A method includes forming Shallow Trench Isolation (STI) regions in a semiconductor substrate and a semiconductor strip between the STI regions. The method also include replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer has a first germanium percentage higher than a second germanium percentage of the second semiconductor layer. The method also includes recessing the STI regions to form semiconductor fins, forming a gate stack over a middle portion of the semiconductor fin, and forming gate spacers on sidewalls of the gate stack. The method further includes forming fin spacers on sidewalls of an end portion of the semiconductor fin, recessing the end portion of the semiconductor fin, and growing an epitaxial region over the end portion of the semiconductor fin.

Fin spacer protected source and drain regions in FinFETs

An integrated circuit can include a MOM capacitor formed simultaneously with other devices, such as finFETs. A dielectric layer formed on a substrate has a first semiconductor fin therein and a second semiconductor fin therein. Respective top portions of the fins are removed to form respective recesses in the dielectric layer. First and second electrodes are formed in the recesses. The first and second electrodes and the interjacent dielectric layer form a MOM capacitor.

Integrated circuit having a MOM capacitor and transistor

A three-dimensional (3D) capacitor includes a semiconductor substrate; one or more fins extending from the semiconductor substrate; an insulator material between each of the one or more fins; a dielectric layer over a first portion of the one or more fins and over the insulator material; a first electrode over the dielectric layer; spacers on sidewalls of the first electrode; and a second electrode over a second portion of the one or more fins and over the insulator material, wherein the first and second portions are different.

3D capacitor based on fin structure having low-resistance surface and method of manufacturing same

A device includes a fin structure protruding over a substrate, wherein the fin structure comprises a plurality of portions formed of different materials, a first carbon doped layer formed between two adjacent portions of the plurality of portions, a second carbon doped layer formed underlying a first source/drain region and a third carbon doped layer formed underlying a second source/drain region.

FinFET structure and method for fabricating the same

A method for forming an antifuse on a substrate is provided, which comprises: forming a first conductive material on the substrate; placing the first conductive material in an electrolytic solution; performing anodic oxidation on the first conductive material to form a nanowire made of the first conductive material and surrounded by a first dielectric material formed during the anodic oxidation and to form the antifuse on the nanowire; and forming a second conductive material on the antifuse to sandwich the antifuse between the first conductive material and the second conductive material.

Antifuse array and method of forming antifuse using anodic oxidation

Growing community of inventors

Hsin-Chu, Taiwan

Chao-Hsiung Wang