Texas Instruments Corporation

Chao-Hsiuan Tsay

Dimitar Trifonov

Tony Ray Larson

Partha Sarathi Basu

Chase Mackenzie Puglisi

Arup Polley

Methods, apparatus, systems, and articles of manufacture are described corresponding to wide bandwidth hall sensing circuitry. An example circuit includes a first hall effect sensor configured to output a first voltage corresponding to a magnetic field; an amplifier to output an amplified voltage by amplifying the first voltage; a second hall effect sensor configured to output a second voltage corresponding to the magnetic field, the second hall effect sensor operating using a spinning technique to toggle a bias current between terminals of the second hall effect sensor, the spinning technique to remove a first offset corresponding to the second hall effect sensor; and offset reduction circuitry configured to: determine a second offset corresponding to the first hall effect sensor based on the first voltage and the second voltage; and generate an output based on the second offset, the amplifier to adjust the amplified voltage based on the output.

Wide bandwidth hall sensing circuitry with offset compensation and gain calibration

A dual integrator system comprises two integrators, an output stage, and a switching network. The first and second integrators receive a differential Hall sensor signal and a reference voltage. The first integrator outputs a first integrator signal based on the differential Hall sensor and the reference voltage. The second integrator outputs a second integrator signal based on the differential Hall sensor signal and the reference voltage. The first integrator comprises a first offset cancellation feedback loop, and the second integrator comprises a second offset cancellation feedback loop. The switching network is coupled to the first and second integrators and to the output stage, and alternates which of the first and second integrators is coupled to the output stage. In some embodiments, the first and second integrators each perform a reset operation, a sampling operation, an integration operation, a differential to single-ended conversion operation, and a holding operation.

Switched capacitor integrator circuit with reference, offset cancellation and differential to single-ended conversion

A system comprises a calibration current generator, which provides a calibration current to a first and a second Hall channel, and a bias current generator, which determines a difference between a calibration signal from the Hall channels and a threshold and adjusts a biasing current for the Hall channels based on the difference. In some embodiments, the bias current generator comprises a subtractor coupled to an ADC and a controller coupled between the ADC and a DAC. The subtractor obtains a first and a second signal from the first and second Hall channels, respectively, and subtracts the first from the second to obtain the calibration signal. The controller determines the difference between a sampled signal from the ADC and the threshold and an adjustment to the biasing current based on the difference. The DAC adjusts the biasing current based on a control signal from the controller indicating the adjustment.

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Tucson, AZ, United States of America

Chao-Hsiuan Tsay