Taiwan Semiconductor Manufacturing Comp. Ltd.

Chao-Hsin Chang

Hsien-Wen Chang

Renn-Shyan Yeh

Chih-Chien Hung

Kuang-Hui Chang

Jiunn-Der Yang

Der-Fang Huang

Wen-Chen Chang

Yung-Fa Lin

Chih-Heng Shen

Tzu-Yu Lin

Chia-Hsiang Chen

Jen-Lin Chao

Edwin Liou

Wei-Kuo Yen

Chi-Shen Lo

Wei-Chuan Huang

Rann Shyan Yeh

Chun-Yi Tsai

Cheng-Hsi Wen

Yu-Fong Tai

In a foundry that produces a product family a system and method of reserving capacity for a pre-process order includes a plurality of products, a common pre-process operation and a plurality of distinct post-process operations corresponding to the products. When a pre-process order related to the pre-process operation from a customer is received, pre-process capacity and post-process operating capacity are reserved according to the pre-process order, and the pre-process capacity is provided for the pre-process. When a post-process order for a product corresponding to a specific post-process operation in the product family is received before a cutoff date, the reserved post-process operating capacity is provided for the corresponding post-process operation. If no post-process order is received before the cutoff date, the reserved post-process operating capacity is released as remnant supply. Other systems and methods are also provided.

System and method of reserving capacity for a pre-process order

Within both a method for controlling microelectronic fabrication production and a system for controlling microelectronic fabrication production there is developed and evaluated for a plurality of microelectronic fabrication facilities a plurality of demand, allocation and output management plans prior to assigning and entering within at least one microelectronic fabrication facility a microelectronic fabrication order. The development and evaluation of the plurality of demand, allocation and output management plans provides for enhanced flexibility when assigning and entering the microelectronic fabrication order.

Microelectronic fabrication production control method and system providing enhanced microelectronic fabrication facility utilization flexibility

Within both a system for managing a work-in-process (WIP) workload within a fabrication facility and a method for managing the work-in-process (WIP) workload within the fabrication facility, there is determined from an overall routing sequence for fabricating the work-in-process (WIP) workload within the fabrication facility a series of routing sub-sequences which correspond with a series of service codes. By using the series of service codes for routing the work-in-process (WIP) workload within the fabrication facility there may be realized operational efficiencies when fabricating the work-in-process (WIP) workload within the fabrication facility.

Service code system and method for scheduling fabrication facility utilization

A method and system provide for yield loss analysis for use in determining the killer stage in the manufacture of a semiconductor wafer at a plurality of manufacturing stages. The method comprising the following steps. Inspect semiconductor devices on the wafer visually to identify the location of visual defects on dies being manufactured on the wafer and to maintain a count of visual defects on the dies by location. Inspect the semiconductor dies on the wafer to determine the location and number defective dies on the wafer at each of the manufacturing stages. Calculate the defective die count for each stage for the wafer. Calculate the defective bad die count for each stage for the wafer. Determine the percentage of the defective bad die count divided by the defective die count. Plot the trend of the percentage of yield loss and the percentage of defective bad dies for each of the manufacturing stages. Compare the plots to determine the killer stage from analysis of the relative trends of matching between the plots of yield lost and the percentage of bad dies for the stage.

Method and system for yield loss analysis by yield management system

A method for determining stress effects, or stress endurance of a film layer coated on a wafer during a scrubber clean process is disclosed. In the method, a wafer having a film layer coated on top is held in a stationary position while a high pressure water jet having a pressure larger than 60 kg/cm,is scanned across a top surface of the film layer and through a center of the wafer. The total number of stress defects is then counted in the scanning path on top of the film layer as an indication of the stress endurance of the specific coating layer. The invention also discloses a method for scrubber cleaning a wafer surface which is coated with a film layer without causing stress defects in the film by rotating a silicon wafer, which has a film layer coated on top at a suitable rotational speed, and then scanning a water jet across a top surface of the film layer without passing through a center of the wafer. The water pressure utilized for the water jet may be suitably between 50 kg/cm,and 75 kg/cm,. It is preferred that the water jet does not pass any regions on the top surface of the film layer that is less than 2 mm from the center of the wafer.

Method for determining stress effect on a film during scrubber clean

A method and metal test pattern for monitoring metal corrosion susceptibility for integrated circuit wafers. Test patterns having an array of metal circles to simulate contact regions, an array of metal strips to simulate electrode regions, and a blanket metal layer to simulate bulk metal regions are formed. A first number of defects per unit area for the test patterns is measured, using a defect scan system. The test pattern wafers are then subjected to environmental stress conditions for a first time and a second number of defects per unit area for the test patterns is measured, again using a defect scan system. The difference between the second number and the first number is compared with a critical number. If excessive corrosion occurs the process for producing wafers is corrected before continuing to process product wafers.

Test pattern for monitoring metal corrosion on integrated circuit wafers

A method for determining a cause for defect formation in an insulating material layer deposited on an electrically conductive layer on a wafer surface is disclosed. In the method, on top of a semi-conducting wafer which has a first insulating material layer deposited, a second insulating material layer is deposited to replace an electrically conductive layer. A third insulating material layer is then deposited on top of the second insulating layer and a water jet which has a high pressure is scanned across a top surface of the third insulating layer with the wafer held in a stationary position. Surface defects are then counted in the predetermined path on the top surface of the third insulating layer for determining the cause for defect formation. When no defects are found, the formation is attributed to electrostatic discharges occurring in the metal conductive layer.

Method for determining a cause for defects in a film deposited on a wafer

The present invention discloses a method for marking a wafer surface with minimized particulate contamination problem and further, the method is compatible with a chemical mechanical polishing method for planarization. An identification mark can be made on the non-patterned side of a wafer by a high energy laser beam either with or without an insulating layer deposited on top of the wafer. The method can also be carried out by first providing an identification mark on a non-patterned surface of the wafer and then, after all fabrication processes have been conducted on the patterned side of the wafer and a planarization process is conducted by a chemical mechanical polishing method, the identification mark on the backside of the wafer can be automatically read and then reproduced on the patterned side of the wafer prior to the shipment of the wafer to a customer or to a packaging facility. The present invention method significantly reduces the particle contamination problem that is frequently caused by laser scribing a silicon surface and furthermore, substantially eliminates the problem that an identification mark becomes illegible after a planarization process by chemical mechanical polishing.

Method for marking a wafer

Method for monitoring metal corrosion on integrated circuit wafers

The present invention provides a method of manufacturing an interlevel dielectric layer (ILD) which has reduced precipitates after an etch back of the borophosphosilicate glass (BPSG) ILD layer. A dielectric layer containing boron and phosphorous is deposited on the substrate. A reflow process is performed on the dielectric layer at a temperature in a range of between about 800.degree. and 950.degree. C. The dielectric layer is etched back using a reactive ion etch. In an important step, a surface treatment is performed on the dielectric layer thorough a plasma treatment. A plasma source gas for the surface treatment is of a gas selected from the group consisting of Ar, NO.sub.2, N.sub.2, and O.sub.2, at a temperature in a range of between about 250.degree. and 400.degree. C. at a pressure in a range of between about 1 mtorr and 5 torr, at a RF power in a range of between about 300 and 400 watts, and for a time in a range of between about 15 and 80 seconds.

Method for reducing precipitate defects using a plasma treatment post

A simple, non critical, low cost process step is added to the manufacture of integrated circuit wafers to remove a ridge of dielectric material remaining at the flat edge of the wafer after an edge rinse has removed the ridge of dielectric from the circular edges of the wafer. A layer of dielectric, such as Spin-On-Glass or the like, is formed on the wafer. An edge rinse is then used to remove the ridge of dielectric formed at the wafer edge, however the edge rinse does not remove the ridge of dielectric at the flat edge of the wafer. A layer of photoresist is formed on the wafer, selectively exposed, and developed to form a photoresist mask. The flat edge of the wafer is then dipped in buffered oxide etch to remove the dielectric material at the flat edge of the wafer. The photoresist mask is then stripped and processing of the wafer is continued. Damage to dielectric material at the flat edge of the wafer, which can cause particles to flake off and become a source of defects in subsequent process steps, in thereby avoided.

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Hsin-Chu, Taiwan

Chao-Hsin Chang