Taiwan Semiconductor Manufacturing Comp. Ltd.

Chao-Ching Cheng

Tzu-Chiang Chen

Hung-Li Chiang

I-Sheng Chen

Yu-Lin Yang

Chun-Chieh Lu

Wei-Sheng Yun

Chen-Feng Hsu

Tung Ying Lee

Lain-Jong Li

Chih Chieh Yeh

Jung-Piao Chiu

Shao-Ming Yu

Yu-Sheng Chen

Yi-Tse Hung

Tzu-Ang Chao

Chih-Hsin Ko

Tsung-Lin Lee

Shih-Syuan Huang

Chih-Chieh Yeh

Ming-Yang Li

Clement Hsingjen Wann

Carlos H Diaz

Chih-Liang Chen

Cheng-Hsien Wu

Ta-Pen Guo

Jin Cai

Tse-An Chen

Szu-Wei Huang

Jer-Fu Wang

Ang-Sheng Chou

Sai-Hooi Yeong

Chi-Feng Huang

Chewn-Pu Jou

Jhon-Jhy Liaw

Huan-Neng Chen

Fu-Lung Hsueh

Kuo-Hua Pan

Tung-Ying Lee

Ta-Chun Lin

Yu-Chao Lin

Tzu-Chung Wang

Chao-Hsien Huang

Hsingjen Wann

Po-Wen Chiu

Han Wang

Kuo-Cheng Chiang

Hou-Yu Chen

Hon-Sum Philip Wong

Chao-Hsin Chien

Yun-Yan Chung

Yee-Chia Yeo

Chih-Sheng Chang

Matthias Passlack

Martin Christopher Holland

Kai-Tai Chang

Timothy Vasen

Ji-Yin Tsai

Gregory Michael Pitner

Yu-sheng Chen

A method of forming a memory device includes the following operations. A first conductive plug is formed within a first dielectric layer over a substrate. A treating process is performed to transform a portion of the first conductive plug into a buffer layer, and the buffer layer caps the remaining portion of the first conductive plug. A phase change layer and a top electrode are sequentially formed over the buffer layer. A second dielectric layer is formed to encapsulate the top electrode and the underlying phase change layer. A second conductive plug is formed within the second dielectric layer and in physical contact with the top electrode. A filamentary bottom electrode is formed within the buffer layer.

Memory devices

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a heat transfer layer disposed over a substrate, a channel material layer, a gate structure and source and drain terminals. The channel material layer has a first surface and a second surface opposite to the first surface, and the channel material layer is disposed on the heat transfer layer with the first surface in contact with the heat transfer layer. The gate structure is disposed above the channel material layer. The source and drain terminals are in contact with the channel material layer and located at two opposite sides of the gate structure.

Semiconductor device

Disclosed herein, in some embodiments, is a memory device. The memory device includes a bottom electrode disposed over a substrate and a top electrode disposed over the bottom electrode. An upper surface of the bottom electrode faces away from the substrate. A bottom surface of the top electrode faces the substrate. A data storage layer is arranged between the bottom electrode and the top electrode. At least a portion of the bottom surface of the top electrode does not overlap with any portion of the top surface of the bottom electrode along a first direction parallel to the bottom surface of the top electrode. Furthermore, at least a portion of the top surface of the bottom electrode does not overlap with any portion of the bottom surface of the top electrode along the first direction.

Data storage element and manufacturing method thereof

Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. In addition, the nanostructures includes channel regions and source/drain regions. The semiconductor structure further includes a gate structure vertically sandwiched the channel regions of the nanostructures and a contact wrapping around and vertically sandwiched between the source/drain regions of the nanostructures.

Semiconductor structure with extended contact structure

A semiconductor device includes a substrate having an I/O region and a core region; a first transistor in the I/O region; and a second transistor in the core region, wherein the first transistor includes a first gate structure having: an interfacial layer; a first high-k region over the interfacial layer; and a conductive layer over the first high-k region, wherein the second transistor includes a second gate structure having: the interfacial layer; a second high-k region over the interfacial layer; and the conductive layer over the second high-k region, and where in the first high-k region is thicker than the second high-k region.

Gate stacks for stack-fin channel I/O devices and nanowire channel core devices

A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional '2D' semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as “metal fin structure”, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.

Forming semiconductor structures with two-dimensional materials

Nanowire devices and fin devices are formed in a first region and a second region of a substrate. To form the devices, alternating layers of a first material and a second material are formed, inner spacers are formed adjacent to the layers of the first material, and then the layers of the first material are removed to form nanowires without removing the layers of the first material within the second region. Gate structures of gate dielectrics and gate electrodes are formed within the first region and the second region in order to form the nanowire devices in the first region and the fin devices in the second region.

Semiconductor device and method

The structure of a semiconductor device with isolation structures between FET devices and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure on a substrate and forming polysilicon gate structures with a first threshold voltage on first fin portions of the fin structure. The method further includes forming doped fin regions with dopants of a first type conductivity on second fin portions of the fin structure, doping at least one of the polysilicon gate structures with dopants of a second type conductivity to adjust the first threshold voltage to a greater second threshold voltage, and replacing at least two of the polysilicon gate structures adjacent to the at least one of the polysilicon gate structures with metal gate structures having a third threshold voltage less than the first and second threshold voltages.

Isolation structures of semiconductor devices

An array of rail structures is formed over a substrate. Each rail structure includes at least one bit line. Dielectric isolation structures straddling the array of rail structures are formed. Line trenches are provided between neighboring pairs of the dielectric isolation structures. A layer stack of a resistive memory material layer and a selector material layer is formed within each of the line trenches. A word line is formed on each of the layer stacks within unfilled volumes of the line trenches. The word lines or at least a subset of the bit lines includes a carbon-based conductive material containing hybridized carbon atoms in a hexagonal arrangement to provide a low resistivity conductive structure. An array of resistive memory elements is formed over the substrate. A plurality of arrays of resistive memory elements may be formed at different levels over the substrate.

Resistive memory devices using a carbon-based conductor line and methods for forming the same

A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The semiconductor device structure includes a gate stack over the substrate and surrounding the first nanostructure. The semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate. The gate stack is between the first source/drain structure and the second source/drain structure. The semiconductor device structure includes an inner spacer layer covering a sidewall of the first source/drain structure and partially between the gate stack and the first source/drain structure. The first nanostructure passes through the inner spacer layer. The semiconductor device structure includes a dielectric structure over the gate stack and extending into the inner spacer layer. The dielectric structure covers a top surface, an inner wall, and a lower surface of the inner spacer layer.

Semiconductor device structure with nanostructure

Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate and spaced apart from each other in a first direction. The semiconductor structure further includes a gate structure wrapping around the nanostructures and a semiconductor layer attached to the nanostructures in a second direction different from the first direction. The semiconductor structure further includes inner spacers sandwiched between the semiconductor layer and the gate structure in the second direction and a silicide layer formed over the semiconductor layer. In addition, a first portion of the semiconductor layer is sandwiched between the inner spacers and the silicide layer in the second direction.

Semiconductor structure with nanostructure

A pellicle for an EUV photo mask includes a first layer; a second layer; and a main layer disposed between the first layer and second layer and including a plurality of nanotubes. At least one of the first layer or the second layer includes a two-dimensional material in which one or more two-dimensional layers are stacked. In one or more of the foregoing and following embodiments, the first layer includes a first two-dimensional material and the second layer includes a second two-dimensional material.

Pellicle for an EUV lithography mask and a method of manufacturing thereof

A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.

Nanowire stack GAA device with inner spacer and methods for producing the same

A semiconductor device includes a substrate, a first poly-material pattern, a first conductive element, a first semiconductor layer, and a first gate structure. The first poly-material pattern is over and protrudes outward from the substrate, wherein the first poly-material pattern includes a first active portion and a first poly-material portion joined to the first active portion. The first conductive element is over the substrate, wherein the first conductive element includes the first poly-material portion and a first metallic conductive portion covering at least one of a top surface and a sidewall of the first poly-material portion. The first semiconductor layer is over the substrate and covers the first active portion of the first poly-material pattern and the first conductive element. The first gate structure is over the first semiconductor layer located within the first active portion.

Semiconductor device and method of manufacturing the same

A method includes: forming a dielectric fin protruding above a substrate; forming a channel layer over an upper surface of the dielectric fin and along first sidewalls of the dielectric fin, the channel layer including a low dimensional material; forming a gate structure over the channel layer; forming metal source/drain regions on opposing sides of the gate structure; forming a channel enhancement layer over the channel layer; and forming a passivation layer over the gate structure, the metal source/drain regions, and the channel enhancement layer.

Fin field-effect transistor device with low-dimensional material and method

Growing community of inventors

Hsinchu, Taiwan

Chao-Ching Cheng