Novatek Microelectronics Corp.

Chao-Chih Hsiao

Yen-Po Chen

Po-Ching Li

Ching-Ho Hung

Min-Chieh Hsu

Ping-Hsun Hsieh

Bor-Chun Wu

Output stage circuit is added to the gate driving circuit of the LCD. The output stage circuit moderates the falling slope of the gate driving signal so as to reduce the feed-through phenomenon. The output stage circuit includes a discharge unit, coupled to a gate line of the gate driving circuit for discharging the gate line to a first supply voltage; a first charge unit, coupled to the gate line of the gate driving circuit for charging the gate line with a second supply voltage; a second charge unit, coupled to the gate line of the gate driving circuit for charging the gate line with the second supply voltage; and a control circuit for controlling the first and the second charge units, and the discharge unit according to a timing controller of the LCD; wherein the control circuit sequentially turns on the first and the second charge units.

Output stage circuit for gate driving circuit in LCD

A gate driving circuit for an LCD device includes a shift register module for generating a plurality of scan signals corresponding to a plurality of channels according to a start signal and a clock signal, a plurality of logic circuits each corresponding to a channel of the plurality of channels, for outputting a driving signal to the channel according to a scan signal of the plurality of scan signals and a shutdown indication signal, and a plurality of shaping and delay units each coupled between two neighboring channels for outputting the shutdown indication signal to another channel after shaping and delaying the shutdown indication signal of a previous stage.

Gate driving circuit and related LCD device capable of separating time for each channel to turn on thin film transistor

Output stage circuit is added to the gate driving circuit of the LCD. The output stage circuit moderates the falling slope of the gate driving signal so as to reduce the feed-through phenomenon. The output stage circuit includes a discharge circuit which discharges the voltage of the gate driving signal with programmable speeds. The discharge circuit has a plurality of discharge units which are turned on sequentially and designed with different driving abilities. At beginning of falling of the gate driving signal, the discharge circuit discharges the gate driving signal with lower driving ability so that the gate driving signal falls with a lower speed. As time passes, the falling speed of the gate driving signal increases by the increasing of the driving ability of the discharge circuit. The entire falling period of the gate driving signal is prolonged by the output stage circuit and the feed-through phenomenon is eased.

A driver apparatus applied on a display is disclosed. The driver apparatus includes a voltage converter, an input level shift circuit, at least one input logic circuit, and at least one output level shifter. The voltage converter receives a first voltage, a ground voltage, and a second voltage, and generates an internal voltage according to the first voltage, the ground voltage, and the second voltage. The input level shift circuit receives an input signal, and generates a level shift input signal transiting between the first voltage and the second voltage according to the input signal. The input logic circuit receives the internal voltage, and generates an internal output signal transiting between the internal voltage and the second voltage according to the level shift input signal. The output level shifter generates a driving signal transiting between a third voltage and the second voltage according to the internal output signal.

Driver apparatus for display

A shift register apparatus is provided. Each of shift registers within the shift register apparatus of the present invention is only constituted by a few of active and passive elements without using conventional digital logic elements, and even the passive element are not required at some conditions. Therefore, the layout area occupied/consumed by each of the shift registers of the present invention is relatively smaller than that of the conventional shift register constituted by a CMOS D-flip-flop, and thus a fabrication cost can be reduced.

Shift register apparatus

A gate driving circuit includes a first output buffer unit region, a level shifter region and a low voltage circuit region. The first output buffer unit region is formed on a plane and is utilized for setting a first output buffer unit. The level shifter region is formed on the plane for setting a level shifter, and includes a vertical region and a horizontal region connected to the vertical region. The vertical region and the first output buffer unit region are aligned in a horizontal direction of the plane. The horizontal region is beneath the vertical region and the first output buffer unit region. The low voltage circuit region is formed on the plane for setting a low voltage circuit, and is beneath the horizontal region. The low voltage circuit region and the horizontal region are aligned in a vertical direction of the plane.

Gate driving circuit

In order to reduce production cost, an output buffer for an electronic device includes a first logic unit, a second logic unit, a first transistor, a second transistor and a control unit. The first logic unit and the second unit are both coupled to an input terminal and conductions of the first logic unit and the second unit are controlled by an input signal from the input terminal. The control unit is coupled to the first logic unit, the second logic unit, the first transistor and the second transistor, for controlling the first transistor and the second transistor to conduct at different times for implementing the non-overlapping function.

Output buffer for an electronic device

A modulation method and a modulation apparatus in a phase-locked loop (PLL) provided. The modulation apparatus comprises a modulator, a crystal oscillator, a controllable R-divisor frequency divider, a controllable N-divisor frequency divider and a voltage-controlled oscillator (VCO). The crystal oscillator generates a fixed frequency oscillating signal. The controllable R-divisor frequency divider receives the oscillating signal from the crystal oscillator and divides the frequency by R. The VCO generates a frequency signal based on a voltage-controlled signal provided by the PLL and feedbacks the frequency signal to the controllable N-divisor frequency divider. The controller N-divisor frequency divider receives a feedback frequency from the VCO and divides the frequency by N. A PLL unit used to compare a frequency provided by the crystal oscillator and passed through the controllable R-divisor frequency divider, with a frequency provided by the VCO and passed through the controllable N-divisor frequency divider, for performing a phase-locked operation.

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Taipei, Taiwan

Chao-Chih Hsiao