Realtek Semiconductor Inc.

Chao-Cheng Lee

Wen-Chi Wang

Jui-Yuan Tsai

Ying-Yao Lin

Tzu-Chien Tzeng

Chia-Jun Chang

Chia-Liang (Leon) Lin

Jui-Cheng Huang

Hong-Yean Hsieh

Jai-Ming Lin

Shih-Wei Wang

Ying-Hsi Lin

Jian-Ru Lin

Chi-Kung Kuan

An-Ming Lee

Han-Chang Kang

Chang-Shun Liu

Horng-Der Chang

Tung-Ming Su

Ren-Chieh Liu

Tzung-Ming Chen

Chia-Liang Chiang

Chieh-Min Feng

Tzung-Hung Kang

Ta-Hsun Yeh

Gerchih Chou

Chien-Ming Wu

Cheng-Chung Hsu

Chen-Chih Huang

Tay-Her Tsaur

Yi-Shu Chang

Ming-Cheng Chiang

Pao-Cheng Chiu

Wen-Shan Wang

Shian-Ru Lin

Wei-Chou Wang

Fong-Ching Huang

Yi-Chih Huang

Chin-Wen Huang

Yung-Ming Chiu

Shih-Yu Ku

Pei-Ju Chiu

Hong Yean Hsieh

Yung-Hao Lin

Yi-Kuang Chen

Guan-Hong Ke

Kuan-Hua Lee

A transmission line driver circuit includes: a transmission line driving amplifier having a first transmission terminal and a second transmission terminal; a first signal node; a second signal node; a first adjustable resistor positioned between the first transmission terminal and the first signal node; a second adjustable resistor positioned between the second transmission terminal and the second signal node; an internal node; a first divider resistor positioned between the first signal node and the internal node; a second divider resistor positioned between the second signal node and the internal node; a comparing circuit for comparing a divided voltage at the internal node with a reference voltage to generate a comparison signal; and an adjusting circuit for adjusting resistance of at least one of the first and second adjustable resistors according to the comparison signal.

Transmission line driver circuit for adaptively calibrating impedance matching

A transmission line driver circuit includes: a transmission line driving amplifier having a first transmission terminal and a second transmission terminal; a first signal node; a second signal node; a first adjustable resistor positioned between the first transmission terminal and the first signal node; a second adjustable resistor positioned between the second transmission terminal and the second signal node; a first voltage difference generating circuit coupled with two terminals of the first adjustable resistor to generate a first voltage difference value; a second voltage difference generating circuit coupled with two terminals of the second adjustable resistor to generate a second voltage difference value; sample-and-hold circuits for generating sampled signals according to the first voltage difference value and the second voltage difference value; a comparing circuit for comparing the sampled signals; and an adjusting circuit for adjusting resistance of the first and/or second adjustable resistors according to the comparing result.

Transmission line driver circuit for automatically calibrating impedance matching

The present invention discloses an integrated circuit having electromagnetic shielding capability and the manufacturing method thereof. An embodiment of the said integrated circuit comprises: a semiconductor circuit structure including a first surface which covers an electromagnetic radiation area; an electromagnetic shielding layer covering the first surface and including at least one contact; and at least one conducting path operable to electrically connect the at least one contact with a steady voltage and thereby shield off the electromagnetic wave from the electromagnetic radiation area, wherein the current running through the electromagnetic shielding layer is zero or less than the maximum current running through the electromagnetic radiation area.

Integrated circuit having electromagnetic shielding capability and manufacturing method thereof

This invention discloses a crystal oscillator, in which by appropriately designing the gain of an amplifier to achieve high trans-conductance and low power consumption. This crystal oscillator includes a first pad, coupled to a first node of a crystal, for receiving a crystal oscillating signal outputted from the crystal; an amplifier, coupled to the first pad, for amplifying the crystal oscillating signal to generate an amplifying signal; an inverter, coupled to the amplifier, for inverting the amplifying signal; and a second pad, coupled to a second node of the crystal, for outputting an oscillating signal to the crystal.

Crystal oscillator

A digitally controlled LC-tank oscillator is constructed by connecting different tuning circuits to a LC tank. The tuning circuit includes a single bank of tuning cells, a dual bank of tuning cells, or a fractional tuning circuit. Each of said tuning cells in the tuning circuit includes a tuning circuit element and a memory cell.

Digitally controlled oscillator

A mixer for the elimination of harmonic mixing in signal transmission is presented. The mixer incorporates a mixing unit and a modulation output unit. The mixing unit receives an input signal and a modulated signal, and outputs an output signal after signal mixing. The modulation output unit is for the generation of modulated signals, which are usually pulse-width modulated. The modulation output unit includes a delta sigma modulator and a digital domain code generator. The delta sigma modulator outputs the modulated signal responding to the received oscillation signal and digital domain code, the digital domain code generator generates the digital domain code in order to provide digital domain sine wave code for the use of the delta sigma modulator. The oscillation signal may be a signal of constant hi-frequency, or a signal that has a frequency larger or equal to that of the input signal by an integer factor.

Harmonic elimination mixer

An equalizer and a related equalizing method for equalizing signal reflection caused by a stub at a transmitting end are provided. The equalizer includes a summing device and a delay device. The summing device is utilized for adding a feedback delay signal to the input signal to generate the equalized signal. The delay device is coupled to the summing device, and utilized for delaying the equalized signal to generate the feedback delay signal. Wherein the delay device has a variable delay time and the variable delay time is a non-integer multiple of a bit time of the input signal.

Equalizer and equalizing method

A successive approximation analog to digital converter and a conversion method thereof are provided. The successive approximation analog to digital converter includes a sample circuit, a conversion circuit, and a filtering control circuit. The sample circuit is configured to sample an analog voltage from an analog signal. The conversion circuit is configured to convert the analog voltage into a digital voltage. The filtering control circuit is configured to transmit a filtering control signal to the sample circuit according to the digital voltage. The sample circuit further samples a next analog voltage from the analog signal and adjusts the next analog voltage into an adjusted analog voltage according to the filtering control signal. The conversion circuit further converts the adjusted analog voltage into a next digital voltage, wherein the next digital voltage is a filtered digital voltage.

Successive approximation analog to digital converter and conversion method thereof

A transmitter for transmitting a transmission signal is disclosed. The transmitter includes: a gain stage, for receiving an input signal and amplifying the input signal according to a gain to generate an amplified signal; and an output stage, coupled to the gain stage, for receiving a first reference voltage signal and the amplified signal and utilizing the first reference voltage signal to perform a predetermined operation on the amplified signal to generate the output signal.

Transmitter for transmitting a transmission signal

This invention provides an equalization apparatus for equalizing an input signal on a cable. The equalization apparatus comprises a cable equalizer for equalizing a cable attenuation effect of the input signal to output a first equalization signal; and a stub equalizer for equalizing a stub effect of the first equalization signal to output an outputting equalization signal.

Equalization apparatus

A reference assisted control system and method thereof are disclosed. The method comprises: receiving a first input signal and a second control signal; generating a first intermediate signal in accordance with a difference between the first input signal and the first output signal; filtering the second control signal to generate a second intermediate signal; performing a weighted sum of the first intermediate signal and the second intermediate signal to generate the control signal; and outputting the first output signal in accordance with the control signal.

Reference assisted control system and method thereof

A clock and data recovery circuit includes a voltage controlled oscillator for generating an output clock according to a control voltage signal, a loop filter for outputting the control voltage signal according to a current output, a charge pump unit for outputting the current output according to an error signal, and a controller for determining a run length corresponding to input data based on the output clock from the voltage controlled oscillator. The controller further controls at least one of the voltage controlled oscillator, the loop filter and the charge pump unit according to the run length to dynamically adjust loop bandwidth. A method of adjusting loop bandwidth is also disclosed.

Clock and data recovery circuit

A receiving device includes a mixer, an AC coupling circuit, a post-stage circuit, and a DC offset calibration circuit. The mixer is utilized for mixing an input signal with a local oscillating (LO) signal from an oscillator to generate a converted signal. The AC coupling circuit is coupled to the mixer and utilized for reducing at least one portion of DC offset of the converted signal to generate a filtered signal. The post-stage circuit is coupled to the AC coupling circuit and utilized for processing the filtered signal to generate an output signal. The DC offset calibration circuit is coupled to the post-stage circuit and utilized for providing at least a compensation current for the post-stage circuit to reduce DC offset of the output signal.

Receiving device and related method for calibrating DC offset

A high linearity mixer circuit includes a commutation network comprising four switches to provide an electrical coupling between a first pair of circuit nodes and a second pair of circuit nodes, whereas the coupling has two states and is controlled by a pair of complementary logical signals. The mixer circuit further comprises a first pair of current-sourcing devices coupled to the first pair of circuit nodes and a second pair of current-sourcing devices coupled to the second pair of circuit nodes. The mixer circuit further includes a pair of capacitors to provide AC coupling, either between the first pair of circuit nodes and a first external circuit, or between the second pair of circuit nodes and a second external circuit.

High linearity passive mixer and method thereof

An apparatus and a method for achieving lock-in of a phase-locked loop (PLL) are disclosed. The PLL receives a reference clock and generates an output clock according to the reference clock. The method comprises: adjusting an oscillation frequency of a controlled oscillator of the PLL close to a desired frequency by counting the number of rising edges of a first clock in a number of a second clock cycles; aligning a rising edge of a third clock and a rising edge of a fourth clock by temporarily changing the oscillation frequency of the digitally controlled oscillator; and locking the phases of the third and fourth clocks by a phase detector of the PLL, wherein the first and the third clocks correspond to the output clock and the second and fourth clocks correspond to the reference clock.

Fast lock-in all-digital phase-locked loop with extended tracking range

Growing community of inventors

Hsin-Chu, Taiwan

Chao-Cheng Lee