Taiwan Semiconductor Manufacturing Comp. Ltd.

Chao-Cheng Chen

Ming-Ching Chang

Chih-Han Lin

Shih-Yao Lin

Ryan Chia-Jen Chen

Yih-Ann Lin

Kuei-Yu Kao

Yu Chao Lin

Syun-Ming Jang Jang

Chun-Hung Lee

Chen-Ping Chen

Jr-Jung Lin

Tzu-Yen Hsieh

Hun-Jan Tao

Tze-Liang Lee

Chia-Shiung Tsai

De-Fang Chen

Yuan-Sheng Huang

Chia Tai Lin

Chih-Tang Peng

Chia-Wei Chang

Jen-Cheng Liu

Chii-Horng Li

Ming-Hsi Yeh

Ming-Hua Yu

Hao-Ming Lien

Chih-Chung Chiu

Hsiao Wen Lee

An-Shen Chang

Ming-Chia Tai

Kuo-Cheng Ching

Bao-Ru Young

Kuei-Shun Chen

Chia-Chu Liu

Hui-Wen Lin

Shih-Hao Lo

Carlos H Diaz

Ming Zhu

Chia-Jen Chen

Yu-Chao Lin

Jin-Aun Ng

Chen-Hua Douglas Yu

Ziwei Fang

Tai-Chun Huang

Jyu-Horng Shieh

Chien-Hao Chen

Tsan-Chun Wang

Kuo-Tai Huang

Harry Hak-Lay Chuang

Hsin-Yi Tsai

Chun-Li Chou

Li-Chih Chao

Jih-Jse Lin

Shun-Hui Yang

Jhon-Jhy Liaw

Mong-Song Liang

Chia-Hao Yu

Chan-Lon Yang

Chia-Hao Hsu

Ming-Huan Tsai

Cheng-Han Wu

Chen-Nan Yeh

Hsin-Chih Chen

Hua Feng Chen

Ming-Jie Huang

Ju-Li Huang

Huang-Ming Chen

Kuo Bin Huang

Jr Jung Lin

Duen-Huei Hou

Shau-Lin Shue

Harry-Hak-Lay Chuang

Shih-Chang Chen

Yung-Cheng Lu

Huan-Just Lin

Weng Chang

Hsueh-Chang Sung

Tsang-Jiuh Wu

Cheng-Ming Wu

Shyh-Chyi Wong

Yu-Hua Lee

Hsien-Hsin Lin

Yu-Chi Lin

Yu-Rung Hsu

Fang-Cheng Chen

Yun-Hung Shen

Tsiao-Chen Wu

Kang-Cheng Lin

Chih Hsuan Wang

Wei-Che Hsieh

Chi-Kang Chang

Yi-Chen Huang

Bi-Ming Yen

Chieh-Ning Feng

Ssu-Pin Ma

Ming-Hsin Huang

Chaochieh Tsai

Han-Guan Chew

Chi-Sheng Lai

Wei-Chung Sun

A fin-type field-effect transistor (FinFET) device includes a plurality of fins formed over a substrate. The semiconductor device further includes a dielectric layer filled in a space between each fin and over a first portion of the plurality of fins and a dielectric trench formed in the dielectric layer. The dielectric trench has a vertical profile. The semiconductor device further includes a second portion of the plurality of fins recessed and exposed in the dielectric trench. The second portion of the plurality of fins have a rounded-convex-shape top profile.

Method of making a FinFET device including a step of removing a portion of a fin

A device includes a substrate, a first fin, a second fin, a first isolation structure, a second isolation structure, and a gate structure. The first fin extends from a p-type region of the substrate. The second fin extends from an n-type region of the substrate. The first isolation structure is over the p-type region and adjacent to the first fin. The first isolation structure has a bottom surface and opposite first and second sidewalls connected to the bottom surface, a first round corner is between the bottom surface and the first sidewall of the first isolation structure, and the first sidewall is substantially parallel to the second sidewall. The second isolation structure is over the n-type region and adjacent to the first fin. The first isolation structure is deeper than the second isolation structure. The gate structure is over the first isolation structure and covering the first fin.

Etch profile control of isolation trench

A semiconductor device includes a fin extending from a substrate, a gate stack over and along a sidewall of the fin, a spacer along a first sidewall of the gate stack and the sidewall of the fin, a dummy gate material along the sidewall of the fin, wherein the dummy gate material is between the spacer and the gate stack, and a first epitaxial source/drain region in the fin and adjacent the gate stack.

FinFET device and method

A method for fabricating a semiconductor device is provided. The method includes forming a fin structure extending along a first lateral direction; forming a dummy gate structure that is over a portion of the fin structure and extends along a second direction perpendicular to the first lateral direction; growing source/drain structures that are respectively coupled to ends of the portion of the fin structure; removing the dummy gate structure to form a gate trench; lining inner sidewalls of the gate trench with a gate spacer; and forming an active gate structure in the gate trench.

Gate structures and spacers in semiconductor devices and methods of manufacturing thereof

In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked over a bottom fin structure protruding from a substrate, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer is formed on an end of each of the etched first semiconductor layers. One or more epitaxial layers are formed in the source/drain space, and the sacrificial gate structure is replaced with a metal gate structure. A width of the source/drain space at a bottommost one of the first semiconductor layers is greater than a width of the source/drain space at one of the first semiconductor layers above the bottommost one of the first semiconductor layers.

Method of manufacturing a semiconductor device and a semiconductor device

A method for fabricating semiconductor devices includes forming a channel structure over a substrate and along a first lateral direction; forming a gate structure extending along a second lateral direction and straddling a portion of the channel structure; forming a gate spacer along a side of the gate structure, the gate spacer having a lateral portion and a vertical portion; growing an epitaxial structure over the channel structure; and forming an air gap within the gate spacer. The air gap is entirely above the epitaxial structure and vertically separated from the epitaxial structure by the lateral portion of the gate spacer.

Semiconductor devices and methods of manufacturing thereof

A semiconductor device includes a substrate. The semiconductor device includes a fin that is formed over the substrate and extends along a first direction. The semiconductor device includes a gate structure that straddles the fin and extends along a second direction perpendicular to the first direction. The semiconductor device includes a first source/drain structure coupled to a first end of the fin along the first direction. The gate structure includes a first portion protruding toward the first source/drain structure along the first direction. A tip edge of the first protruded portion is vertically above a bottom surface of the gate structure.

A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate electrode over the fin; removing lower portions of the dummy gate electrode proximate to the isolation regions, where after removing the lower portions, there is a gap between the isolation regions and a lower surface of the dummy gate electrode facing the isolation regions; filling the gap with a gate fill material; after filling the gap, forming gate spacers along sidewalls of the dummy gate electrode and along sidewalls of the gate fill material; and replacing the dummy gate electrode and the gate fill material with a metal.

Fin field-effect transistor device and method of forming the same

A device includes a fin protruding from a semiconductor substrate; a gate stack over and along a sidewall of the fin; a gate spacer along a sidewall of the gate stack and along the sidewall of the fin; an epitaxial source/drain region in the fin and adjacent the gate spacer; and a corner spacer between the gate stack and the gate spacer, wherein the corner spacer extends along the sidewall of the fin, wherein a first region between the gate stack and the sidewall of the fin is free of the corner spacer, wherein a second region between the gate stack and the gate spacer is free of the corner spacer.

Method of manufacturing a semiconductor device having corner spacers adjacent a fin sidewall

A cyclic process including an etching process, a passivation process, and a pumping out process is provided to prevent over etching of the sacrificial gate electrode, particularly when near a high-k dielectric feature. The cyclic process solves the problems of failed gate electrode layer at an end of channel region and enlarges filling windows for replacement gate structures, thus improving channel control. Compared to state-of-art solutions, embodiments of the present disclosure also enlarge volume of source/drain regions, thus improving device performance.

Semiconductor devices and methods of fabrication thereof

A device includes a substrate, a channel layer, a gate structure, a first source/drain epitaxial structure, a second source/drain epitaxial structure, and a bottom dielectric structure. The channel layer is over the substrate. The gate structure is across the channel layer. The first source/drain epitaxial structure and the second source/drain epitaxial structure are on opposite sides of the channel layer and are connected to the channel layer. The bottom dielectric structure is between the first source/drain epitaxial structure and the substrate. A maximum width of the first source/drain epitaxial structure is greater than or equal to a maximum width of the bottom dielectric structure in a cross-sectional view.

Semiconductor device and manufacturing method thereof

A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate over the fin; reducing a thickness of a lower portion of the dummy gate proximate to the isolation regions, where after reducing the thickness, a distance between opposing sidewalls of the lower portion of the dummy gate decreases as the dummy gate extends toward the isolation regions; after reducing the thickness, forming a gate fill material along at least the opposing sidewalls of the lower portion of the dummy gate; forming gate spacers along sidewalls of the dummy gate and along sidewalls of the gate fill material; and replacing the dummy gate with a metal gate.

FinFET device having a gate with a tapering bottom portion and a gate fill material with a widening bottom portion

Semiconductor device structures with a gate structure having different profiles at different portions of the gate structure may include a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.

Gate structure with non-linear profile for transistors

A semiconductor device includes a plurality of channel layers vertically separated from one another. The semiconductor device also includes an active gate structure comprising a lower portion and an upper portion. The lower portion wraps around each of the plurality of channel layers. The semiconductor device further includes a gate spacer extending along a sidewall of the upper portion of the active gate structure. The gate spacer has a bottom surface. Moreover, a dummy gate dielectric layer is disposed between the gate spacer and a topmost channel layer of plurality of channel layers. The dummy gate dielectric layer is in contact with a top surface of the topmost channel layer, the bottom surface of the gate spacer, and the sidewall of the gate structure.

Semiconductor devices including dummy gate dielectric layer and methods of manufacturing thereof

A method of fabricating a semiconductor structure includes selective use of a cladding layer during the fabrication process to provide critical dimension uniformity. The cladding layer can be formed before forming a recess in an active channel structure or can be formed after filling a recess in an active channel structure with dielectric material. These techniques can be used in semiconductor structures such as gate-all-around (GAA) transistor structures implemented in an integrated circuit.

Process window control for gate formation in semiconductor devices

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Hsin-Chu, Taiwan

Chao-Cheng Chen