Mostek Corporation

Dallas Semiconductor Corporation

Chao C Mai

Tsiu Chiu Chan

Francis A Scherpenberg

William M Gosney, Jr

Wayne Mendenhall

Myint Hswe

Donald J Gulyas

Titkuan Hui

William M Whitney

A system comprising a card device for effectuating a transaction when presented to a transaction terminal, the card device including a memory and a first energy source, the source for powering the memory for a period of time, and a card cradle carrier for storing the card device when the card device is not engaged in the transaction. The card cradle carrier is formed of a substantially rigid material and forms at least a portion of a personal effect. In accordance with the teachings of the present invention, the card cradle carrier includes a second energy source for recharging the first energy source when the card device is received for storage by the card cradle carrier.

Card cradle system and method

A method for making a semiconductor device is described in which overlapping polycrystalline silicon layers are deposited over selected portions of a semiconductor substrate and insulated from the substrate and from each other, thereby providing an improved semiconductor device for use in a random-access memory integrated circuit.

Method for making a semiconductor device

A method of forming a plurality of interconnected metal oxide semiconductor field effect transistors on P-type semiconductor substrate (10). A layer of oxide (14) is formed on the substrate (10) and then a polysilicon layer (16) is formed on top of the oxide layer (14). A layer of silicon nitride (18) is deposited on top of the polysilicon layer (16). The silicon nitride layer (18), polysilicon layer (16) and oxide layer (14) are selectively etched to form a conductor pattern. The conductor pattern defines a gate electrode and a plurality of interconnecting lines (42) that interconnect transistors to each other and to the peripheral circuits that drive the transistors. The source and drain regions (26 and 28) are ion implanted with arsenic ions. The exposed sidewalls of the polysilicon layer (16) are oxidized lateral and subjacent to the silicon nitride layer (18). The oxidation forms a lateral band of oxide (32) on the polysilicon layer (16) and effectively reduces the conductive width of the polysilicon layer (16). The reduced conductive width reduces the overlap capacitance. The silicon nitride layer (18) is then removed and a layer of tungsten (34) is deposited by hot-wall, low-pressure chemical vapor deposition (LPCVD). The tungsten layer (34) selectively adheres to the polysilicon layer (18) providing a low resistance path for the conductors. The tungsten layer (18) forms both a gate electrode and the low resistance interconnect lines (42) or 'runs.' A heat treatment may then be applied to the combined tungsten layer (34) and the polysilicon layer (16) to form a composite conductor of tungsten silicide. Thereafter the interconnect lines (42) and gate electrodes are covered by a low temperature oxide (36).

MOSFET Fabrication process for reducing overlap capacitance and lowering

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Dallas, TX, United States of America

Chao C Mai