Shanghai Huali Integrated Circuit Corporation

Chanyuan Hu

Liyao Liu

Yingju Chen

Yenchan Chiu

Jianxun Chen

Xiumei Hu

Changhung Kung

Ting Ye

Xiantao Li

Jhencyuan Li

A method for cutting off a fin in a field effect transistor, comprising: stepforming fins and first spacing regions, there are two types of fins&#x2014;the first type is configured to be cut off and a second type is configured to be reserved; and forming a first material layer to fill the first spacing regions; stepforming a first pattern structure comprising first strip structures aligning to one first type fin and second spacing regions; stepforming second sidewalls on two sides of each first strip structure; stepremoving the first strip structures to form a second pattern structure by the second sidewalls; stepetching away the first material layer and the first type of fins by using the second sidewalls as a mask ; stepremoving the second sidewalls and the remaining first material layer. The present application enables using less advanced lithography equipment.

Method for cutting off FIN field effect transistor

The present disclosure discloses a FinFET transistor cut etching process method, comprising: step 1, forming a first photoresist pattern to define a cut etching region of the FinFET transistor; step 2, forming a second amorphous semiconductor pattern; step 3, forming a first dielectric layer and a first groove; step 4, forming a second dielectric layer that fully fills the first groove; step 5, performing CMP using the second amorphous semiconductor layer as a stop layer, so as to form a sidewall and a second dielectric layer strip; step 6, performing self-alignment to remove each side wall; step 7, performing a wet process to remove the amorphous semiconductor strip; and step 8: performing etching by using each second dielectric layer strip as a mask, so as to form a fin and achieve cut etching of the FinFET transistor. The present disclosure can enlarge the process window and reduce the process cost.

FinFET transistor cut etching process method

A method for manufacturing a semiconductor device comprising: providing a substrate, wherein an amorphous silicon layer is formed on the substrate; forming an etching auxiliary layer on the amorphous silicon layer, wherein the upper surface of the etching auxiliary layer is flat, and the etching auxiliary layer is made of a single material; and etching the amorphous silicon layer and the etching auxiliary layer to obtain an amorphous silicon layer with a target thickness, wherein the upper surface of the etched amorphous silicon layer is flat.

Method for manufacturing semiconductor device

A method for manufacturing a semiconductor device comprising: providing a substrate, wherein a first gate structure corresponding to a dense area transistor and a second gate structure corresponding to an isolated area transistor are formed on the substrate, and the first gate structure is higher than the second gate structure; forming a buffer layer over the second gate structure, wherein the upper surface of the buffer layer is flush with the upper surface of the first gate structure; and removing the top of the first gate structure, and forming a hard mask filling layer on a top area of the first gate structure.

The disclosure provides a method for making a self-aligned double pattern, A silicon substrate with a first oxide layer, an amorphous silicon layer and an organic layer, etching the organic layer and the amorphous silicon layer, and covering them with a first silicon nitride layer; remove the first silicon nitride layer in the amorphous silicon pattern, forming first silicon nitride sidewall patterns on the amorphous silicon pattern's sidewalls; removing the amorphous silicon pattern between the first silicon nitride sidewall patterns; defining the morphology of a fin field-effect transistor, form core patterns and covering them with a thin silicon nitride layer; depositing a second oxide layer; defining the fin field-effect transistor's height, and etching back the second oxide layer till the height of the core patterns satisfies the defined fin field-effect transistor height; removing the thin silicon nitride layer, depositing a third oxide layer to cover the core patterns.

Method for making self-aligned double pattern

This disclosure discloses a process method for cutting a polysilicon gate of a FinFET transistor, comprising: step, forming a fin and a first groove in a polysilicon gate formation region and forming a second groove in a non-polysilicon gate region; step, performing filing with a first insulating layer; step, performing definition by using a second photomask opposite to a first photomask that defines a polysilicon gate cutting region, and forming a first mask on the top of the first insulating layer in the second groove; step, performing etching-back of the first insulating layer to define the height of the fin; step, forming a polysilicon gate; and step, after the polysilicon gate cutting region is opened by using the first photomask, performing polysilicon etching to achieve cutting of the polysilicon gate. In the present disclosure, the process window is enlarged, thereby increasing the product yield.

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Shanghai, China

Chanyuan Hu