Samsung Electronics Co., Ltd.

Chanyoung Jeong

Wooseok Kim

Wonsik Yu

Taeik Kim

Jusung Lee

Kangyeop Choo

Junhyeok Yang

Insung Kim

Dokyung Lim

Sunghyuck Lee

Sounghun Shin

A device includes an oscillator including at least one inductor and at least one capacitor and configured to generate, based on a positive supply voltage, an output signal oscillating in a resonance frequency of the at least one inductor and the at least one capacitor. The device further includes an oscillation detector configured to determine whether the output signal oscillates based on a clock signal and increase a loop gain of the oscillator until the output signal oscillates.

Device and method for adaptive loop gain of oscillator

A monitoring circuit for a high frequency signal includes: a phase locked loop configured to generate a divided output signal with respect to an input signal based on a plurality of dividers; a plurality of dividing monitoring circuits configured to receive dividing input signals and dividing output signals respectively corresponding to the plurality of dividers, and output dividing error signals; and a jitter monitoring circuit configured to output a jitter error signal.

Monitoring circuit of phase locked loop and operating method thereof

A frequency-locked loop (FLL) logic circuit, including a validity signal generator configured to receive an external clock signal and determine whether a glitch occurs in the external clock signal; a clock divider configured to generate a reference frequency clock signal based on the external clock signal and a determination result of the validity signal generator; a synchronizer configured to synchronize a phase of an oscillator clock signal with a phase of the reference frequency clock signal; a clock counter configured to count a number of pulses of the oscillator clock signal during a reference time; and a code limiter configured to determine a range of a frequency selection value for calibrating an operating frequency of the oscillator clock signal based on the counted number of pulses.

Oscillation system including frequency-locked loop logic circuit and operating method thereof

A bandgap reference circuit includes a reference current generation circuit configured to output a bandgap reference current insensitive to a temperature change, by using a first voltage inversely proportional to temperature and a third voltage proportional to temperature. The third voltage is a difference between the first voltage and a second voltage. The bandgap reference circuit further includes a resistivity temperature coefficient cancellation circuit configured to remove a first current proportional to temperature from the bandgap reference current by using the third voltage, and a reference voltage generation circuit configured to output a bandgap reference voltage insensitive to a temperature change by using a second current inversely proportional to temperature and a first resistance proportional to temperature. The second current is generated by removing the first current from the bandgap reference current.

Bandgap reference circuit including resistivity temperature coefficient cancellation circuit, and oscillator circuit including the bandgap reference circuit

A digitally controlled oscillator (DCO) includes; a current mirror configured to generate a supply current in response to a bias voltage matching a reference current, a variable resistor connected to the current mirror through a first node outputting the reference current and configured to provide a variable resistance in response to a first control signal, an oscillation circuit connected to the current mirror through a second node outputting the supply current and configured to generate an oscillation signal in response to the supply current, and a feedback circuit configured to control the bias voltage in relation to at least one of a voltage at the first node and a voltage at the second node.

Digitally controlled oscillator insensitive to changes in process, voltage, temperature and digital phase locked loop including same

A phased locked loop includes; a load circuit that generates an output signal in response to a driving voltage, a frequency calibration circuit that generates a calibration signal in response to an output frequency of the output signal and a target frequency, and a regulator that generates the driving voltage in response to the calibration signal.

Growing community of inventors

Hwaseong-si, South Korea

Chanyoung Jeong