Soitec

Asm America, Inc.

Arizona State University

Tokyo Electron Limited

Commissariat a L'energie Atomique

S.o.i.tec Silicon on Insulator Technologies

S.o.i. Tec Silicon on Insulator Technologies, S.a.

Lawrence Semiconductor Research Laboratory, Inc.

Asm Nutool, Inc.

Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.v.

Chantal Arena

Pierre Tomasini

Ed Lindow

Subhash Mahajan

Paul D Brabant

Michael Albert Tischler

Bulent Mehmet Basol

Bruno Ghyselen

Ivo Johannes Raaijmakers

Robert Daniel Clark

Christiaan J Werkhoven

Ronald Thomas Bertram, Jr

Matthias Bauer

Nyles Wynn Cody

Joseph P Italiano

Jean-Philippe Debray

Heather McFavilen

Ilsu Han

Ranjan Datta

Joseph T Hillman

Ronald T Bertram

Fabrice Letertre

Ding Ding

Robin Scott

Nupur Bhargava

Ronald Bertram

Carlos Mazure

Keith Doran Weeks

Robert F Foster

Laurent Clavelier

Charles Michael Birtcher

Thomas Andrew Steidl

Andrew David Johnson

Dennis L Goodwin

Frank Dimroth

Patrice Noel

Li Huang

Emmanuel Guidotti

Richard Scott Kern

Claudio Canizares

Alec Fischer

Marc Rabarot

Ismail Emesh

Jean-Pierre Joly

Michael S Ameen

Paul T Jacobson

Fred Newman

Joe P Italiano

Vasil Vorsa

Chris Werkhoven

Michel Papapietro

Rahul Ajay Trivedi

Ron Bertram

Fanyu Meng

Jacques Faguet

Heather McFelea

Frank Reinhardt

Andreas W Bett

A free-standing microstructure may be formed from an engineered substrate including a first silicon layer, a second silicon layer, and an intermediate layer. The second silicon layer may include a monocrystalline silicon film. The intermediate layer may be between the first silicon layer and the second silicon layer. The intermediate layer may include a silicon- or germanium-based material having a different lattice constant than the first silicon layer or the second silicon layer. The intermediate layer of the free-standing microstructure may further include one or more voids wherein at least a portion of the silicon- or germanium-based material is absent between the first silicon layer and the second silicon layer.

Engineered substrates, free-standing semiconductor microstructures, and related systems and methods

A method of fabricating a semiconductor structure includes the formation of a first bonding layer at least substantially comprised of a first III-V material on a major surface of a first element, and formation of a second bonding layer at least substantially comprised of a second III-V material on a major surface of a second element. The first bonding layer and the second bonding layer are disposed between the first element and the second element, and the first element and the second element are attached to one another at a bonding interface disposed between the first bonding layer and the second bonding layer. Semiconductor structures are fabricated using such methods.

Semiconductor structures including bonding layers, multi-junction photovoltaic cells and related methods

Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InGaN, and at least one barrier layer comprising InGaN proximate the at least one well layer. In some embodiments, the value of w in the InGaN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InGaN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light-emitting device, such as an LED. Luminary devices include such LEDs.

Semiconductor structures having active regions comprising InGaN and methods of forming such semiconductor structures

Methods of fabricating semiconductor devices or structures include bonding a layer of semiconductor material to another material at a temperature, and subsequently changing the temperature of the layer of semiconductor material. The another material may be selected to exhibit a coefficient of thermal expansion such that, as the temperature of the layer of semiconductor material is changed, a controlled and/or selected lattice parameter is imparted to or retained in the layer of semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a layer of semiconductor material having an average lattice parameter at room temperature proximate an average lattice parameter of the layer of semiconductor material previously attained at an elevated temperature.

Methods of fabricating semiconductor structures or devices using layers of semiconductor material having selected or controlled lattice parameters

Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InGaN, and at least one barrier layer comprising InGaN proximate the at least one well layer. In some embodiments, the value of w in the InGaN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InGaN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.

Semiconductor structures having active regions including indium gallium nitride, methods of forming such semiconductor structures, and related light emitting devices

The invention relates to methods and apparatus that are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically GaN wafers. Specifically, the methods relate to substantially preventing the formation of unwanted materials on an isolation valve fixture within a chemical vapor deposition (CVD) reactor. The invention provides apparatus and methods for limiting deposition/condensation of GaCland reaction by-products on an isolation valve that is used in the system and method for forming a monocrystalline Group III-V semiconductor material by reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber.

Equipment for high volume manufacture of group III-V semiconductor materials

A system for epitaxial deposition of a Group III-V semiconductor material that includes gallium. The system includes sources of the reactants, one of which is a gaseous Group III precursor having one or more gaseous gallium precursors and another of which is a gaseous Group V component, a reaction chamber wherein the reactants combine to deposit Group III-V semiconductor material, and one or more heating structures for heating the gaseous Group III precursors prior to reacting to a temperature to decompose substantially all dimers, trimers or other molecular variations of such precursors into their monomer forms.

Gallium trichloride injection scheme

The present invention provides improved gas injectors for use with CVD (chemical vapor deposition) systems that thermalize gases prior to injection into a CVD chamber. The provided injectors are configured to increase gas flow times through heated zones and include gas-conducting conduits that lengthen gas residency times in the heated zones. The provided injectors also have outlet ports sized, shaped, and arranged to inject gases in selected flow patterns. The invention also provides CVD systems using the provided thermalizing gas injectors. The present invention has particular application to high-volume manufacturing of GaN substrates.

Gas injectors including a funnel- or wedge-shaped channel for chemical vapor deposition (CVD) systems and CVD systems with the same

Embodiments of the invention include methods for forming Group III-nitride semiconductor structure using a halide vapor phase epitaxy (HVPE) process. The methods include forming a continuous Group III-nitride nucleation layer on a surface of a non-native growth substrate, the continuous Group III-nitride nucleation layer concealing the upper surface of the non-native growth substrate. Forming the continuous Group III-nitride nucleation layer may include forming a Group III-nitride layer and thermally treating said Group III-nitride layer. Methods may further include forming a further Group III-nitride layer upon the continuous Group III-nitride nucleation layer.

Methods for forming group III-nitride materials and structures formed by such methods

Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer, and at least one barrier layer proximate the at least one well layer. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.

Semiconductor structures having active regions comprising InGaN, methods of forming such semiconductor structures, and light emitting devices formed from such semiconductor structures

Methods of fabricating semiconductor devices or structures include forming structures of a semiconductor material overlying a layer of a compliant material, subsequently changing the viscosity of the compliant material to relax the semiconductor material structures, and utilizing the relaxed semiconductor material structures as a seed layer in forming a continuous layer of relaxed semiconductor material. In some embodiments, the layer of semiconductor material may comprise a III-V type semiconductor material, such as, for example, indium gallium nitride. Novel intermediate structures are formed during such methods. Engineered substrates include a continuous layer of semiconductor material having a relaxed lattice structure.

Semiconductor structures, devices and engineered substrates including layers of semiconductor material having reduced lattice strain

Atomic layer deposition (ALD) or ALD-like deposition processes are used to fabricate dilute nitride III-V semiconductor materials. A first composition of process gases may be caused to flow into a deposition chamber, and a group V element other than nitrogen and one or more group III elements may be adsorbed over the substrate (in atomic or molecular form). Afterward, a second composition of process gases may be caused to flow into the deposition chamber, and N and one or more group III elements may be adsorbed over the substrate in the deposition chamber. An epitaxial layer of dilute nitride III-V semiconductor material may be formed over the substrate in the deposition chamber from the sequentially adsorbed elements.

Methods of forming dilute nitride materials for use in photoactive devices and related structures

Dilute nitride III-V semiconductor materials may be formed by substituting As atoms for some N atoms within a previously formed nitride material to transform at least a portion of the previously formed nitride material into a dilute nitride III-V semiconductor material that includes arsenic. Such methods may be employed in the fabrication of photoactive devices, such as photovoltaic cells and photoemitters. The methods may be carried out within a deposition chamber, such as a metalorganic chemical vapor deposition (MOCVD) or a hydride vapor phase epitaxy (HVPE) chamber.

Methods of fabricating dilute nitride semiconductor materials for use in photoactive devices and related structures

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Mesa, AZ, United States of America

Chantal Arena