Taiwan Semiconductor Manufacturing Comp. Ltd.

Chansyun David Yang

Keh-Jeng Chang

Chan-Lon Yang

Li-Te S Lin

Pinyen Lin

Perng-Fei Yuh

Han-Yu Lin

Fang-Wei Lee

Tze-Chung Lin

Fo-Ju Lin

Yih Wang

Meng-Sheng Chang

Ku-Feng Lin

Jui-Che Tsai

Yoshitaka Yamauchi

Shao-Ting Wu

Tzu-hsien Yang

Yu-Wei Lin

Philex Ming-yan Fan

Shao-yu Chou

Chung-Liang Cheng

Tzer-Min Shen

Hsiang-Pi Chang

Chih-Ching Wang

Yao-Sheng Huang

Gwan-Sin Chang

Chun-Yu Chen

Yen-Tien Tung

Huang-Lin Chao

Yu-Chia Liang

Shen-Yang Lee

A method for fabricating an integrated circuit device is provided. The method includes forming a transistor device over a front side of the semiconductor substrate; forming a first contact feature in the semiconductor substrate, wherein the first contact feature is connected with a back side of a first source/drain feature of the transistor device; and forming a memory structure over a back side of the first contact feature facing away from the first source/drain feature.

Method for fabricating an integrated circuit comprising devices on opposing sides of a substrate

The present disclosure describes a method to form a stacked semiconductor device with power rails. The method includes forming the stacked semiconductor device on a first surface of a substrate. The stacked semiconductor device includes a first fin structure, an isolation structure on the first fin structure, and a second fin structure above the first fin structure and in contact with the isolation structure. The first fin structure includes a first source/drain (S/D) region, and the second fin structure includes a second S/D region. The method also includes etching a second surface of the substrate and a portion of the first S/D region or the second S/D region to form an opening. The second surface is opposite to the first surface. The method further includes forming a dielectric barrier in the opening and forming an S/D contact in the opening.

Power rails for stacked semiconductor device

A semiconductor device includes a channel layer, an interfacial layer, a gate dielectric layer, a gate electrode, dipole elements, and additional elements. The interfacial layer is disposed on the channel layer, and includes an insulating material. The gate dielectric layer is disposed over the interfacial layer such that the channel layer is separated from the gate dielectric layer by the interfacial layer. The gate electrode is disposed on the gate dielectric layer. The dipole elements are present in at least one of the interfacial layer and the gate dielectric layer in a predetermined amount such that the semiconductor device has a predetermined threshold voltage. The additional elements are located at a region where the dipole elements are present so as to reduce interfacial defects caused by the dipole elements. The additional elements are different from the dipole elements. Methods for manufacturing the semiconductor device are also disclosed.

Semiconductor device with tunable threshold voltage and method for manufacturing the same

A method for treating a semiconductor structure includes: disposing the semiconductor structure in a chamber; introducing a modifying agent into the chamber to modify a surface part of a dielectric element; and introducing a removing agent into the chamber while applying an electromagnetic radiation with a selected frequency to the chamber so as to permit the dielectric element to be selectively heated by the electromagnetic radiation to have a temperature higher than those of other elements of the semiconductor structure, and so as to permit the modified surface part of the dielectric element to be removed.

Method for selectively removing predetermined part of selected element in semiconductor structure

A method for generating an extreme ultraviolet (EUV) radiation includes simultaneously irradiating two or more target droplets with laser light in an EUV radiation source apparatus to produce EUV radiation and collecting and directing the EUV radiation produced from the two or more target droplet by an imaging mirror.

Method of manufacturing integrated circuit

The present disclosure describes methods and systems for radical-activated etching of a metal oxide. The system includes a chamber, a wafer holder configured to hold a wafer with a metal oxide disposed thereon, a first gas line fluidly connected to the chamber and configured to deliver a gas to the chamber, a plasma generator configured to generate a plasma from the gas, a grid system between the plasma generator and the wafer holder and configured to increase a kinetic energy of ions from the plasma, a neutralizer between the grid system and the wafer holder and configured to generate electrons and neutralize the ions to generate radicals, and a second gas line fluidly connected to the chamber and configured to deliver a precursor across the wafer. The radicals facilitate etching of the metal oxide by the precursor.

Radical-activated etching of metal oxides

A semiconductor device structure is provided. The semiconductor device structure includes forming semiconductor device structure includes a gate stack wrapping around a plurality of nanowire structures. The gate stack includes a first portion above the plurality of nanowire structures and second portions between the nanowire structures. The semiconductor device structure further includes a gate spacer layer along a sidewall of the first portion of the gate stack, and a plurality of inner spacer layers along sidewalls of the second portions of the gate stack. The gate spacer layer has a first carbon concentration, the inner spacer layers have a second carbon concentration, and the second carbon concentration is lower than the first carbon concentration.

Semiconductor device structure with inner spacer layer

The structure of a semiconductor device with negative capacitance (NC) dielectric structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure with a fin base portion and a fin top portion on a substrate, forming a spacer structure in a first region of the fin top portion, and forming a gate structure on a second region of the fin top portion. The spacer structure includes a first NC dielectric material and the gate structure includes a gate dielectric layer with a second NC dielectric material different from the first NC dielectric material.

Field effect transistor with negative capacitance dielectric structures

A method for forming a semiconductor structure includes forming a fin on a semiconductor substrate. The fin includes channel layers and sacrificial layers stacked one on top of the other in an alternating fashion. The method also includes removing a portion of the fin to form a first opening and expose vertical sidewalls of the channel layers and the sacrificial layers, epitaxially growing a source/drain feature in the first opening from the exposed vertical sidewalls of the channel layers and the sacrificial layers, removing another portion of the fin to form a second opening to expose a vertical sidewall of the source/drain feature, depositing a dielectric layer in the second opening to cover the exposed vertical sidewall of the source/drain feature, and replacing the sacrificial layers with a metal gate structure in the second opening. The dielectric layer separates the source/drain feature from contacting the metal gate structure.

Inner spacer formation in multi-gate transistors

The present disclosure describes a semiconductor device includes a first fin structure, an isolation structure in contact with a top surface of the first fin structure, a substrate layer in contact with the isolation structure, an epitaxial layer in contact with the isolation structure and the substrate layer, and a second fin structure above the first fin structure and in contact with the epitaxial layer.

Independent control of stacked semiconductor device

The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

Memory devices, semiconductor devices, and methods of operations a memory device

An apparatus includes a beam conditioning assembly configured to output one or more wavelengths to a substrate being processed and receive one or more reflected wavelengths from the substrate, and a machine learning device configured to process the one or more reflected wavelengths to predict a process variable and compare the predicted process variable with a measured process variable to obtain a comparison result.

Interferometer systems and methods for real time etch process compensation control

A semiconductor device with different configurations of nanostructured channel regions and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a fin structure disposed on a substrate, a stack of nanostructured horizontal channel (NHC) regions disposed on the fin structure, a nanostructured vertical channel (NVC) region disposed within the stack of NHC regions, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the NHC regions and on portions of the NVC region that are not covered by the NHC regions and the fin structure.

Nanostructured channel regions for semiconductor devices

The present disclosure describes a method includes forming a fin structure including a fin base portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer on the fin base portion, a second semiconductor layer above the first semiconductor layer, and a sacrificial semiconductor layer between the first and second semiconductor layers. The method further includes replacing the sacrificial semiconductor layer with a negative capacitance (NC) layer and forming gate electrodes around the NC layer, the first semiconductor layer, and the second semiconductor layer. The NC layer includes an NC dielectric material.

Field effect transistors with negative capacitance layers

A semiconductor device with different configurations of gate structures and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes a stack of nanostructured channel regions disposed on a fin structure, a first gate structure disposed within the stack of nanostructured channel regions, a second gate structure surrounds the first gate structure about a first axis and surrounds the nanostructured channel regions about a second axis different from the first axis, and first and second contact structures disposed on the first and second gate structures, respectively.

Growing community of inventors

Shinchu, Taiwan

Chansyun David Yang