International Business Machines Corporation

Globalfoundries Inc.

Infineon Technologies Ag

Globalfoundries U.S. Inc.

Other

Adeia Semiconductor Bonding Technologies Inc.

Altis Semiconductor, Snc

Altis Semiconductor

Adeia Semiconductor Solutions LLC

Atlis Semiconductor

Chanro Park

Ruilong Xie

Kangguo Cheng

Min Gyu Sung

Hoon Sik Kim

Julien Frougier

Juntao Li

Koichi Motoyama

Chih-Chao Yang

Kenneth Chun Kuen Cheng

Hui Zang

Lars W Liebmann

Laertis Economikos

Steven J Bentley

Andre P Labonte

Hsueh-Chung Chen

Tenko Yamashita

Kwan-Yong Lim

Yann Mignot

Daniel Chanemougame

Choonghyun Lee

Son Van Nguyen

Andrew Mark Greene

Sanjay C Mehta

Alexander Reznicek

Veeraraghavan S Basker

Nicolas J Loubet

Soon-Cheon Seo

Heng Wu

Su Chen Fan

Kisik Choi

Nicholas Anthony Lanzillo

Guillaume Bouche

Christopher Joseph Waskiewicz

Yi Qi

Eric Gerhard Liniger

Brent A Anderson

John H Zhang

Balasubramanian Pranatharthiharan

Xiuyu Cai

Injo Ok

Xunyuan Zhang

Cheng Chi

Wolfgang Raberg

Vimal Kumar Kamineni

William James Taylor, Jr

Lei Sun

Ryan Ryoung-Han Kim

Steven R Soss

Edward J Nowak

Lawrence Alfred Clevenger

Haiting Wang

Jiehui Shu

Gerard M Schmid

Chun-Chen Yeh

Shesh Mani Pandey

Haigou Huang

Michael C Gaidis

Murat Kerem Akarvardar

Ulrich Karl Klostermann

Naim Moumen

Somnath Ghosh

Gregory Costrini

Takashi Ando

Junli Wang

Peng Xu

Chen Zhang

Oleg Gluschenkov

Dechao Guo

Shom Ponoth

Ajey Poovannummoottil Jacob

Sivananda K Kanakasabapathy

Ruqiang Bao

Reinaldo Ariel Vega

Christopher J Penny

Ekmini Anuja De Silva

Eugene John O'Sullivan

David William Abraham

Siva P Adusumilli

Hosadurga K Shobha

Chi-Chun Liu

John Ryan Sporre

Xuefeng Liu

Xusheng Kevin Wu

Muthumanickam Sankarapandian

Stuart A Sieg

Yongan Xu

Errol Todd Ryan

Andy C Wei

Lan Yu

Victor Chan

John A Iacoponi

Huai Huang

Huimei Zhou

Nicholas V Licausi

Roderick Alan Augur

Jay William Strane

Daniel J Jaeger

Wenhui Wang

Sean Xuan Lin

An interconnect structure and a method of forming the interconnect structure are provided. The interconnect structure includes a source drain contact above and contacting a source drain region of a semiconductor device. The interconnect structure also includes a via above and contacting the source drain contact. The via includes a lower portion with an uppermost surface that contacts a lowermost surface of an interlayer dielectric.

Liner-less via contact

A semiconductor includes a first GAA FET and second GAA FET. The second GAA FET includes a first gate dielectric and second gate dielectric within its gate structure. The first GAA FET includes just the first gate dielectric within its gate structure. The gate dielectric structure of the first GAA FET provides for a nominal or a lesser effective gate dielectric or gate dielectric resistance relative to an effective gate dielectric structure of the second GAA FET. The first GAA FET further includes a first gate conductor within its gate structure and the second GAA FET further includes the first gate conductor and a second gate conductor within its gate structure. The first gate conductor and the second gate conductor are separated by the second gate dielectric.

Heterogeneous gate all around dielectric thickness

A method, apparatus, and manufacturing system are disclosed herein for a vertical field effect transistor patterned in a self-aligned process. A plurality of fins is formed. A gate structure is formed on at least a first side and a second side of a lower portion of each fin. A spacer is formed on at least a first side and a second side of an upper portion of each fin. At least one layer is formed above the substrate and between the fins. An opening is formed in the at least one layer between the fins by an etching process. The spacer protects the gate structure during the etching process.

Methods, apparatus, and manufacturing system for self-aligned patterning of a vertical transistor

A memory device including a trench to a first electrically conductive structure; a first electrode of a conformal electrically conductive material contained within the trench in electrical communication with the first electrically conductive structure and is present on sidewalls of the trench; a switching layer is present in the trench on the first electrode and extends outside the trench; and a second electrode present on the switching layer overfilling the trench. The memory device also includes a contact positioned on a portion of the second electrode that is overfilling the trench to provide that the contact is horizontally offset from the first electrode that is present in the trench.

Top contact on resistive random access memory

A first metal interconnection pattern is formed over a substrate. A spacer layer is selectively deposited on the exposed surfaces of the first metal interconnection pattern. Subsequently, a metal overburden layer is deposited on the spacer layer. The excess portion of the metal overburden layer is removed, i.e., that portion deposited over a top surface of the metal interconnection pattern and the spacer layer. This forms a second metal interconnection pattern. The elements of the second metal interconnection pattern are located between respective elements of the first metal interconnection pattern.

Double patterning with selectively deposited spacer

An integrated circuit (IC) is provided. The IC includes a substrate that includes first and second channels. A shared source or drain (S/D) region is between the first and second channels. The shared source or drain region includes an uppermost surface and further includes a second surface recessed from the uppermost surface and sidewalls extending from the uppermost surface to the second surface to define a recess. First and second gate structures including gate metal are disposed on the first and second channels. An S/D wrap-around contact (WAC) includes a first portion which extends into the recess to contact the second surface and the sidewalls and is wrapped around the S/D region at an exterior of the recess.

Non-self-aligned wrap-around contact in a tight gate pitched transistor

A semiconductor structure having a backside contact structure with increased contact area includes a plurality of source/drain regions within a field effect transistor, each of the plurality of source/drain regions includes a top portion having an inverted V-shaped area. A backside power rail is electrically connected to at least one source/drain region through a backside metal contact. The backside metal contact wraps around a top portion of the at least one source/drain region. A tip of the top portion of the plurality of source/drain regions points towards the backside power rail with the top portion of the at least one source/drain region being in electric contact with the backside metal contact. A first epitaxial layer is in contact with a top portion of at least another source/drain region adjacent to the at least one source/drain region for electrically isolating the at least another source/drain region from the backside power rail.

Semiconductor backside contact structure with increased contact area

A buried power rail contact structure is provided that wraps around a source/drain region of a first field effect transistor (FET), contacts a surface of a buried power rail, and has a reduced height as compared to a height of a neighboring source/drain contact structure that contacts a surface of a source/drain region of a second FET. Both the buried power rail contact structure and the source/drain contact structure have a negative taper, i.e., each of the buried power rail contact structure and the source/drain contact structure has outermost sidewalls that slope outward from a topmost surface of the contact structure to a bottommost surface of the contact structure. Such contact structures reduce the parasitic capacitance between a functional gate structure and the contact structure.

Buried power rail with robust connection to a wrap around contact

A semiconductor device includes one or more fins extending from a substrate, the one or more fins having source/drain epitaxial grown material (S/D epitaxy) thereon that merges one or more fins, a gate formed over the one or more fins, the gate including high k metal gate disposed between gate spacers and a metal liner over the S/D epitaxy and sides of the gate spacers. The gate includes a self-aligned contact cap over the HKMG and the metal liner.

Formation of trench silicide source or drain contacts without gate damage

A semiconductor structure includes a backside contact, and an unmerged source/drain region. The backside contact is wrapped-around the unmerged source/drain region.

Semiconductor structure with wrapped-around backside contact

A semiconductor structure including a first metal line, a top via above and directly contacting the first metal line, a second metal line adjacent to the first metal line, a first dielectric contacting sidewalls of the top via, a second dielectric directly between the first dielectric and the second metal line, and an air gap located between the first metal line and the second metal line, and below both the first dielectric and the second dielectric.

Top via interconnect with airgap

The structure comprises a first low-k dielectric layer on top of a substrate. The structure comprises one or more trenches within the first low-k dielectric layer. The structure comprises a first barrier layer on the first low-k dielectric layer, a first liner layer on top of the first barrier layer and a first metal layer on top of the first liner layer, wherein a top of the first barrier layer, the first liner layer, and the first metal layer are at least 5 nm below a top of the first low-k dielectric layer. The structure comprises a dielectric cap between portions the first low-k dielectric layer and a second low-k dielectric layer. The structure comprises a dielectric plug between portions of the first low-k dielectric layer and the second low-dielectric layer.

Dual-damascene fav interconnects with dielectric plug

Disclosed is a memory device. The memory device comprises a cross-bar array of memory cells. The cross-bar array of memory cells comprises a plurality of bottom level lines arranged in a first direction. The cross-bar array of memory cells further comprises a plurality of vias arranged on top of each of the plurality of bottom level lines. The cross-bar array of memory cells further comprises a plurality of memory cells. Each memory cell is arranged on top of one of the plurality of vias. The cross-bar array of memory cells further comprises a plurality of top level lines arranged in a second direction that is substantially perpendicular to the first direction. Each top level line is arranged on top of and electrically connected to two or more memory cells.

Top via containing random-access memory cross-bar array

A method including forming a plurality of nanosheet layers on a substrate and forming a plurality of first sacrificial layers on the substrate, wherein the plurality of nanosheet layers and the plurality of first sacrificial layers are arranged in alternating layers, where the plurality of first sacrificial layers is comprised of a first material. Selectively removing the plurality of first sacrificial layers and forming a plurality of second sacrificial layers where the plurality of first sacrificial layers were removed, where the plurality of second sacrificial layers is comprised of a second material, where the first material and the second material are different. Recessing the plurality of second sacrificial layers at an even rate.

Method to release nano sheet after nano sheet fin recess

Embodiments of the invention include a transistor coupled to a memory element, the memory element being in series with a first bistable resistive element that is configured to switch between a first low resistance state and a first high resistance state. A logic circuit is coupled to the transistor via a series connection to a second bistable resistive element, the second bistable resistive element being configured to switch between a second low resistance state and a second high resistance state.

Circuit architecture using transistors with dynamic dual functionality for logic and embedded memory drivers

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Clifton Park, NY, United States of America

Chanro Park