International Business Machines Corporation

Globalfoundries Inc.

Infineon Technologies Ag

Globalfoundries U.S. Inc.

Other

Adeia Semiconductor Bonding Technologies Inc.

Altis Semiconductor, Snc

Altis Semiconductor

Adeia Semiconductor Solutions LLC

Atlis Semiconductor

Chanro Park

Ruilong Xie

Kangguo Cheng

Min Gyu Sung

Hoon Sik Kim

Julien Frougier

Juntao Li

Koichi Motoyama

Chih-Chao Yang

Lars W Liebmann

Steven J Bentley

Hui Zang

Laertis Economikos

Andre P Labonte

Hsueh-Chung Chen

Tenko Yamashita

Kwan-Yong Lim

Yann Mignot

Daniel Chanemougame

Choonghyun Lee

Son Van Nguyen

Sanjay C Mehta

Alexander Reznicek

Nicolas J Loubet

Heng Wu

Andrew Mark Greene

Su Chen Fan

Kisik Choi

Guillaume Bouche

Nicholas Anthony Lanzillo

Christopher Joseph Waskiewicz

Yi Qi

Eric Gerhard Liniger

Brent A Anderson

Veeraraghavan S Basker

John H Zhang

Balasubramanian Pranatharthiharan

Soon-Cheon Seo

Xiuyu Cai

Injo Ok

Xunyuan Zhang

Cheng Chi

Wolfgang Raberg

Vimal Kumar Kamineni

William James Taylor, Jr

Lei Sun

Ryan Ryoung-Han Kim

Steven R Soss

Edward J Nowak

Lawrence Alfred Clevenger

Haiting Wang

Jiehui Shu

Gerard M Schmid

Chun-Chen Yeh

Shesh Mani Pandey

Haigou Huang

Michael C Gaidis

Murat Kerem Akarvardar

Ulrich Karl Klostermann

Naim Moumen

Gregory Costrini

Somnath Ghosh

Takashi Ando

Junli Wang

Peng Xu

Chen Zhang

Oleg Gluschenkov

Dechao Guo

Shom Ponoth

Ajey Poovannummoottil Jacob

Sivananda K Kanakasabapathy

Ruqiang Bao

Christopher J Penny

Reinaldo Ariel Vega

Ekmini Anuja De Silva

Eugene John O'Sullivan

David William Abraham

Siva P Adusumilli

Chi-Chun Liu

Hosadurga K Shobha

John Ryan Sporre

Xuefeng Liu

Xusheng Kevin Wu

Muthumanickam Sankarapandian

Stuart A Sieg

Yongan Xu

Errol Todd Ryan

Andy C Wei

Victor Chan

Lan Yu

John A Iacoponi

Huai Huang

Nicholas V Licausi

Huimei Zhou

Roderick Alan Augur

Jay William Strane

Daniel J Jaeger

Wenhui Wang

Sean Xuan Lin

Arunava Gupta

A semiconductor structure including a first metal line, a top via above and directly contacting the first metal line, a second metal line adjacent to the first metal line, a first dielectric contacting sidewalls of the top via, a second dielectric directly between the first dielectric and the second metal line, and an air gap located between the first metal line and the second metal line, and below both the first dielectric and the second dielectric.

Top via interconnect with airgap

The structure comprises a first low-k dielectric layer on top of a substrate. The structure comprises one or more trenches within the first low-k dielectric layer. The structure comprises a first barrier layer on the first low-k dielectric layer, a first liner layer on top of the first barrier layer and a first metal layer on top of the first liner layer, wherein a top of the first barrier layer, the first liner layer, and the first metal layer are at least 5 nm below a top of the first low-k dielectric layer. The structure comprises a dielectric cap between portions the first low-k dielectric layer and a second low-k dielectric layer. The structure comprises a dielectric plug between portions of the first low-k dielectric layer and the second low-dielectric layer.

Dual-damascene fav interconnects with dielectric plug

Disclosed is a memory device. The memory device comprises a cross-bar array of memory cells. The cross-bar array of memory cells comprises a plurality of bottom level lines arranged in a first direction. The cross-bar array of memory cells further comprises a plurality of vias arranged on top of each of the plurality of bottom level lines. The cross-bar array of memory cells further comprises a plurality of memory cells. Each memory cell is arranged on top of one of the plurality of vias. The cross-bar array of memory cells further comprises a plurality of top level lines arranged in a second direction that is substantially perpendicular to the first direction. Each top level line is arranged on top of and electrically connected to two or more memory cells.

Top via containing random-access memory cross-bar array

A method including forming a plurality of nanosheet layers on a substrate and forming a plurality of first sacrificial layers on the substrate, wherein the plurality of nanosheet layers and the plurality of first sacrificial layers are arranged in alternating layers, where the plurality of first sacrificial layers is comprised of a first material. Selectively removing the plurality of first sacrificial layers and forming a plurality of second sacrificial layers where the plurality of first sacrificial layers were removed, where the plurality of second sacrificial layers is comprised of a second material, where the first material and the second material are different. Recessing the plurality of second sacrificial layers at an even rate.

Method to release nano sheet after nano sheet fin recess

Embodiments of the invention include a transistor coupled to a memory element, the memory element being in series with a first bistable resistive element that is configured to switch between a first low resistance state and a first high resistance state. A logic circuit is coupled to the transistor via a series connection to a second bistable resistive element, the second bistable resistive element being configured to switch between a second low resistance state and a second high resistance state.

Circuit architecture using transistors with dynamic dual functionality for logic and embedded memory drivers

A resistive random access memory (ReRAM) device is provided. The ReRAM device includes a first electrode including a first conductive layer sandwiching a second conductive layer, the second conductive layer being wider than the first conductive layer; a resistive switching element layer formed in contact with sidewalls of the first electrode, a first portion of the resistive switching element layer that is in contact with the sidewalls of the first conductive layer having a width that is greater than a second portion of the resistive switching element layer that is in contact with the sidewalls of the second conductive layer; and a second electrode that is in contact with the resistive switching element layer.

Resistive switching memory cell

Semiconductor structures having an increased gate length are provided by providing a vertical stack of suspended semiconductor channel material nanosheets that include a middle portion located between a first end portion and a second end portion. The middle portion of each suspended semiconductor channel material nanosheet is vertically offset from (i.e., higher or lower than) the first end portion and the second end portion of each suspended semiconductor channel material nanosheet.

Increased gate length at given footprint for nanosheet device

A method for forming a semiconductor device includes forming a structure having at least a first nanosheet stack for a first device, a second nanosheet stack for a second device and disposed over the first nanosheet stack, a disposable gate structure, and a gate spacer. The disposable gate structure and sacrificial layers of the first and second nanosheet stacks are removed thereby forming a plurality of cavities. A conformal gate dielectric layer is formed in the plurality cavities and surrounding at least portions of the first and second nanosheet stacks. A first conformal work function layer is formed in contact with the gate dielectric layer. Portions of the first conformal work function layer are removed without using a mask from at least the second nanosheet stack. A second conformal work function layer is formed on exposed portions of the gate dielectric layer.

Vertical stacked nanosheet CMOS transistors with different work function metals

Embodiments herein describe FETs with channels connected on the sides to a metal liner. To avoid the difficulties of connecting the sides of the channels to metal liners for the drain and source regions, the embodiments herein form a male/female contact between the channels and the metal liners. In one embodiment, instead of exposing only the end or side surfaces of the channels, an end knob of the channel is exposed. This knob can include the side surface as well as a portion of the top, bottom, front, and back sides of the channel. As such, when the metal liner is deposited on the knob, this metal forms an electrical connection on all sides of the knob. This male/female connection provides a more reliable and lower resistance connection between the channel and the metal liner than using only the end or side surfaces of the channel.

Wrap-around-contact for 2D-channel gate-all-around field-effect-transistors

A semiconductor device is provided. The semiconductor device includes a memory including a bottom electrode, a magnetic tunnel junction (MTJ) stack on the bottom electrode, and an upper electrode on the MTJ stack. The semiconductor device also includes at least one dielectric layer formed around the memory, wherein a top metal layer contact hole is formed in the at least one dielectric layer, a dielectric liner layer formed in the top metal contact hole, and a top metal layer contact in the top metal layer contact hole.

MRAM top electrode structure with liner layer

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a dynamic random-access-memory (DRAM), and the DRAM includes a vertical transistor and a nanosheet transistor, the vertical transistor being stacked on top of the nanosheet transistor, where a bottom source/drain of the vertical transistor is directly above and connected to a gate of the nanosheet transistor through a conductive via. A method of manufacturing the semiconductor structure is also provided.

Scaled 2T DRAM

A MIM capacitor and related methods of fabricating the MIM capacitor. The MIM capacitor includes a bottom capacitor plate including a plurality of trenches defined therein, and a top capacitor plate. The MIM capacitor also includes a capacitor insulating layer disposed between the top capacitor plate and the bottom capacitor plate and within the plurality of trenches. Further, the MIM capacitor includes a first electrode electrically connected to the bottom capacitor plate, and a second electrode electrically connected to the top capacitor plate.

Metal-insulator-metal capacitor structure with enlarged capacitor area

A copper interconnect with self-aligned hourglass-shaped metal cap comprises a plurality of interconnect lines formed in a dielectric layer of a semiconductor device. The copper interconnect further comprises a metal cap formed on top of each interconnect line of the plurality of interconnect lines, where the metal cap is formed with self-aligning concave sides extending from a top surface of the dielectric layer to a top surface of the metal cap.

Copper interconnects with self-aligned hourglass-shaped metal cap

A fin stack including compressively strained and tensile-strained semiconductor fin regions allows CMOS fabrication to form vertically stacked p-type FinFETs and n-type FinFETs. Aspect ratio trapping within a semiconductor base region within the fin stack provides a relaxed semiconductor base region on which uniaxially strained regions are grown. A dielectric layer may be formed to electrically isolate the compressively strained semiconductor fin region from the tensile-strained semiconductor fin region.

Fin stack including tensile-strained and compressively strained fin portions

A semiconductor structure is presented including source/drain (S/D) epitaxial growth formed over a bottom dielectric isolation region, at least one first semiconductor layer disposed within the S/D epitaxial growth in a S/D region and at least one second semiconductor layer disposed partially within a gate region. The at least one second semiconductor layer extends from the gate region into a spacer region to enable a connection to the S/D epitaxial growth. The semiconductor structure further includes a first region with adjacent devices exhibiting a first Contacted gate Poly Pitch (CPP) defining a first gate-to-gate space and a second region with adjacent devices exhibiting a second CPP defining a second gate-to-gate space, where adjacent devices exhibiting the first CPP have a smaller gate-to-gate canyon than the adjacent devices exhibiting the second CPP such that the second gate-to-gate space is greater than the first gate-to-gate space.

CPP-agnostic source-drain contact formation for gate-all-around devices with dielectric isolation

Growing community of inventors

Clifton Park, NY, United States of America

Chanro Park