Nxp Usa, Inc.

Freescale Semiocnductor, Inc.

Chanpreet Singh

Michael Andreas Staudenmaier

Kshitij Bajaj

Rahul Jain

Gaurav Gupta

Stephan Matthias Herrmann

Vincent Aubineau

Sharath Subramanya Naidu

Tejbal Prasad

Pranshu Agrawal

Navarshi Dhiman

Abhineet Kumar Bhojak

Anisha Ladsaria

Nakul Grover

A system-on-chip (SoC) includes first and second processing circuits and a data exchange circuit such that the first processing circuit is configured to process image lines based on corresponding sets of processing attributes. The first processing circuit is further configured to continuously receive and process the image lines one after the other to generate corresponding output data, and the second processing circuit is configured to continuously receive by way of the data exchange circuit, the generated output data for processing the generated output data. The data exchange circuit is thus configured to control data flow between the first processing circuit and the second processing circuit such that the first processing circuit and the second processing circuit parallelly process corresponding data associated with same or different image lines.

System for parallelly processing image lines from multiple image sensors

A system for processing multiple images includes an access serializer, trigger controllers, a first-in-first-out (FIFO) memory, and an image signal processing (ISP) pipeline circuit. The access serializer serializes access requests that are associated with processing of input image lines of the images. The trigger controllers decode corresponding serialized access requests to generate trigger identifiers (IDs), respectively. The FIFO memory receives a corresponding trigger ID from each trigger controller and provides the trigger IDs to the ISP pipeline circuit based on an order of reception of the trigger IDs. The ISP pipeline circuit receives the input image lines associated with the trigger IDs, and based on a corresponding set of configuration parameters associated with the input image lines, processes the input image lines in an order of reception of the trigger IDs, to generate processed image lines, respectively.

System for processing images from multiple image sensors

Embodiments are disclosed that apply adaptive sub-tiles to captured images for distortion correction in vision-based assistance systems and methods. A captured image is processed to generate corrected tiles, and selected numbers of sub-tiles are used to generate each of the corrected tiles depending upon the pixel densities for regions of the captured image. The corrected sub-tiles are combined to form corrected tiles, and corrected tiles are combined for form a corrected image. The corrected image can be used to output control signals to cause actions to be issued to a user of the system such as a driver of a vehicle. For one embodiment, the corrected tiles are generated one at a time, and corrected sub-tiles for each corrected tile are also generated one at a time based upon individual source data blocks determined by a pre-determined sub-tile configuration. Efficient memory use and data transfers are provided.

Adaptive sub-tiles for distortion correction in vision-based assistance systems and methods

A layer selection module for a graphics display component, and method therefor. The layer selection module is arranged to identify a set M of active layers to be blended for a pixel, configure a display controller to generate composite pixel data for the pixel based on a subset N of up to n layers from the set M, determine whether a number m of active layers in the set M exceeds n, and output an indication of which active layers within the set M were excluded from the subset N, if it is determined that the number m of layers in the set M exceeds n.

Method and apparatus for managing graphics layers within a graphics display component

A script-driven head-up display controller comprising an image warping unit and an image projection unit wherein the image warping unit is coupled to the image projection unit and is adapted to:

Head-up display warping controller

The present application relates to a display controller and display system and a method of operating thereof. At a filtering stage display image data are generated on the basis of received pixel-mapped image data. The filtering operation accepts a plurality of pixels out of the received image data as input values to generate a pixel of the display image data as output value. It is further determined whether the plurality of pixels being the input values to the filtering operation are marked. If all pixels thereof are marked, the output pixel being the output value is marked. The marked pixels in the display image data are validated on the basis reference data.

Display controller, heads-up image display system and method thereof

An asynchronous data transfer system includes a bus interface unit (BIU), a FIFO write logic module, a write pointer synchronizer, a write pointer validator, a FIFO read logic module, and an asynchronous FIFO buffer. The FIFO buffer receives a variable size data from the BIU and stores the variable size data at a write address. The FIFO write logic module generates a write pointer by encoding the write address using a Johnson code. The FIFO read logic module receives a synchronized write pointer at the asynchronous clock domain and generates a read address signal when the synchronized write pointer is a valid Johnson code format. The FIFO buffer transfers the variable size data to a processor based on the read address signal.

Asynchronous FIFO buffer with Johnson code write pointer

A display controller includes first and second arbitrating units, a pixel data calculating unit, a latency measurement unit, and a clock divider. The first and second arbitrating units fetch first and second pixel data corresponding to at least one pixel from an external memory via a system bus. The pixel data calculating unit determines a size of the first and second pixel data. The latency measuring unit generates a first data rate value that is indicative of a latency of the system bus based on the size of the first and second pixel data. The clock divider receives a first clock signal modulation value corresponding to the first data rate value and alters a modulation of a reference clock signal. The graphics blending unit receives the first and second pixel data and provides blended pixel data to a display panel based on a modulated clock signal.

Growing community of inventors

S.A.S. Nagar, India

Chanpreet Singh