Samsung Electronics Co., Ltd.

Chanmi Lee

Ji-Hye Lee

Nam-Gun Kim

Joonkyu Rhee

Taeseop Choi

Sangwuk Park

Sanggyo Chung

Yejeong Seo

A semiconductor memory device includes a stack structure including word lines and interlayer dielectric patterns that are alternately and repeatedly stacked on a semiconductor substrate. Semiconductor patterns are respectively disposed between vertically adjacent word lines. A bit line vertically extends from the semiconductor substrate and contacts the semiconductor patterns. A capping insulating pattern is disposed between the bit line and the word lines and covers side surfaces of the interlayer dielectric patterns. Memory elements are respectively disposed between vertically adjacent interlayer dielectric patterns. Each of the semiconductor patterns comprises a first source/drain region that contacts the bit line, a second source/drain region that directly contacts one memory element of the memory elements, and a channel region between the first and second source/drain regions. A largest width of the first source/drain region is greater than a width of the channel region.

Semiconductor memory device and method of fabricating the same

Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a plurality of bit lines running across the active region in a second direction crossing the first direction, a first spacer on a sidewall of the bit line, and a storage node contact on the active region between adjacent bit lines. The first spacer includes a first part between the storage node contact and the bit line, a second part between the first part and the storage node contact, and a third part between the first and second parts. A minimum vertical thickness of the first part is greater than a maximum vertical thickness of the third part. The maximum vertical thickness of the third part is greater than a maximum vertical thickness of the second part.

Semiconductor devices

Semiconductor devices and method of manufacturing the same are provided. The devices may include a substrate including a first impurity region and second impurity regions spaced apart from the first impurity region and a conductive line. The conductive line may extend in a first direction and may be electrically connected to the first impurity region. The devices may also include first conductive contacts on a side of the conductive line and arranged in the first direction and first insulation patterns on the side of the conductive line and arranged in the first direction. The first conductive contacts may be electrically connected to the second impurity regions. The first conductive contacts and the first insulation patterns may be alternately disposed along the first direction. Top surfaces of the first insulation patterns may be lower than a top surface of the conductive line relative to an upper surface of the substrate.

Semiconductor devices including conductive contacts and insulation patterns arranged in an alternating sequence and methods of fabricating the same

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Suwon-si, South Korea

Chanmi Lee