Samsung Electronics Co., Ltd.

Chankyung Kim

Uksong Kang

Soo-Ho Cha

Sungchul Park

Youngjin Cho

Sungyong Seo

Kwangchol Choe

Sun-Young Lim

Seongil O

JinHyeok Choi

Duckhyun Chang

Taehyun Kim

Nam Sung Kim

Sang Woo Lee

Junsoo Kim

Woo Bin Song

Minhee Cho

Hei Seung Kim

Sangwuk Park

Hoyoung Song

Jaehong Min

Ho Young Lee

Sang-won Shim

Suk-Soo Pyo

Sanguhn Cha

Jongpil Son

Ho Dong Lee

Dong-seok Kang

Seongui Seo

Sangbo Lee

Seonghyun Jeon

Soo Hwan Kim

Yunsang Lee

Sangjung Jeon

Mijo Kim

Yonggyu Chu

Seungbum Ko

A resistive memory device includes a resistive cell connected between a first bit line and a first source line, a reference cell including a reference resistor and connected between a second bit line and a second source line, and a write driver connected to the first bit line or the first source line, connected to the second bit line or the second source line. The write driver includes a comparator configured to compare previous data written in the resistive cell with the target data by comparing a voltage of the first source line with a voltage of the second source line or comparing a voltage of the first bit line with a voltage of the second bit line, and determine whether the target data is written in the resistive cell after comparing the previous data with the target data.

Resistive memory device for writing data and operating method thereof

A semiconductor device can include a semiconductor substrate and an active region in the semiconductor substrate, where the active region can include an oxide semiconductor material having a variable atomic concentration of oxygen. A first source/drain region can be in the active region, where the first source/drain region can have a first atomic concentration of oxygen in the oxide semiconductor material. A second source/drain region can be in the active region spaced apart from first source/drain region and a channel region can be in the active region between the first source/drain region and the second source/drain region, where the channel region can have a second atomic concentration of oxygen in the oxide semiconductor material that is less than the first atomic concentration of oxygen. A gate electrode can be on the channel region and extend between the first source/drain region and the second source/drain region.

Method of forming a semiconductor device including an active region with variable atomic concentration of oxide semiconductor material

A nonvolatile memory device includes a nonvolatile memory, a volatile memory being a cache memory of the nonvolatile memory, and a first controller configured to control the nonvolatile memory. The nonvolatile memory device further includes a second controller configured to receive a device write command and an address, and transmit, to the volatile memory through a first bus, a first read command and the address and a first write command and the address sequentially, and transmit a second write command and the address to the first controller through a second bus, in response to the reception of the device write command and the address.

Nonvolatile memory device and operation method thereof

An operating method of a storage device which includes a first nonvolatile memory device and a second nonvolatile memory device includes detecting sudden power-off, suspending an operation being performed in the first nonvolatile memory device, in response to the detected sudden power-off, writing suspension information about the suspended operation into the second nonvolatile memory device, and performing a block management operation on the first nonvolatile memory device based on the suspension information written into the second nonvolatile memory device, in power-up after the sudden power-off.

Storage device and operating method thereof

A memory device including: a memory cell array including a memory cell, the memory cell configured to store first data based on a first write current; a write driver configured to output the first write current based on a control value; and a current controller including a replica memory cell, the current controller configured to generate the control value based on a state of second data which is stored in the replica memory cell, wherein an intensity of the first write current is adjusted based on the control value.

Memory device operating based on a write current for a given operation condition and a method of driving the write current

Semiconductor device including active region with variable atomic concentration of oxide semiconductor material and method of forming the same

A memory device includes a memory cell array that a plurality of memory cells, an edge buffer circuit that is placed in a first region adjacent to one side of the memory cell array and receives an external signal from the outside through a pad, and a middle buffer circuit that is placed in a second region adjacent to an opposite side of the memory cell array and receives a differential small-swing signal corresponding to the external signal from the edge buffer circuit through first and second signal lines above the memory cell array. The edge buffer circuit drives the first and second signal lines based on the external signal such that the differential small-swing signal is transmitted to the middle buffer circuit.

Memory device, memory system and electronic device

Disclosed is a memory device which includes a first memory cell connected to a word line and a first bit line, a second memory cell connected to the word line and a second bit line, and a row decoder selecting the word line, a row decoder configured to select the word line, and a column decoder. A first distance between the row decoder and the first memory cell is shorter than a second distance between the row decoder and the second memory cell. The column decoder selects the first bit line based on a time point when the first memory cell is activated.

Memory device with improved latency and operating method thereof

Memory devices may include a memory cell connected to a word line and a bit line, a first bit line sense amplifier connected to the memory cell through the bit line and configured to amplify a signal of the bit line, and a second bit line sense amplifier disposed adjacent to the first bit line sense amplifier and not connected to the bit line. The second bit line sense amplifier may be selected by an address received from a processor, and data may be stored in the second bit line sense amplifier or the data is output from the second bit line sense amplifier according to a command received from the processor. In some aspects described herein, the memory device may include a buffer memory that operates at high speed, thereby increasing performance of a memory module.

Memory device using sense amplifiers as buffer memory with reduced access time and method of cache operation of the same

Disclosed are a memory device, a memory package including the same, and a memory module including the same. The memory package includes a first memory device configured to operate in response to a first chip select signal from an external device, a second memory device configured to operate in response to a second chip select signal from the external device, and a third memory device configured to operate in response to a third chip select signal from the external device. The third memory device includes a buffer unit that is connected with an internal circuit of the third memory device through an internal data line, is connected with the first memory device through a first memory data line, is connected with the second memory device through a second memory data line, and is connected with the external device through a data line.

Memory device, memory package including the same, and memory module including the same

A memory device includes a first memory cell, a second memory cell, a third memory cell, a bitline sense amplifier, and a switch circuit. The first memory cell is connected to a first wordline and a first bitline. The second memory cell is connected to the first wordline and a second bitline. The third memory cell is connected to the first wordline and a third bitline. The bitline sense amplifier is connected to the third bitline. The switch circuit is connected to the first bitline, the second bitline, and the bitline sense amplifier. The switch circuit performs charge sharing between the first memory cell and the first bitline to generate a first reference voltage, and charge sharing between the second memory cell and the second bitline to generate a second reference voltage.

Memory device including memory cell for generating reference voltage

Disclosed is a memory package. The memory package includes a nonvolatile memory chip, a volatile memory chip of which an access speed is faster than an access speed of the nonvolatile memory chip, and a logic chip for performing a refresh operation about the volatile memory chip in response to a refresh command from an external device, and migrating at least a portion of data stored in the nonvolatile memory chip to the volatile memory chip when the refresh operation is performed.

Memory package, memory module including the same, and operation method of memory package

A method includes outputting, at a processor, a command and an address to the memory module, receiving match/unmatch bits indicating results of comparing a tag corresponding to the address with tags stored in the memory module, from the memory module, determining, at the processor, a cache hit/miss from the match/unmatch bits by using majority voting, and outputting, at the processor, the determined cache hit/miss to the memory module.

Memory module, computing system having the same, and method for testing tag error thereof

Growing community of inventors

Hwaseong-si, South Korea

Chankyung Kim