Samsung Electronics Co., Ltd.

Dell Products Inc.

Korea Advanced Institute of Science and Technology

Chanik Park

Moonwook Oh

Kangho Roh

Hojun Shim

Wonmoon Cheon

Wonhee Cho

Yang-sup Lee

Jong Tae Park

Je-Hyuck Song

Youngjoon Choi

Seontaek Kim

Jaesoo Lee

Seung-Duk Cho

Jaehoon Heo

Jisoo Kim

Insu Choi

Wonjae Shin

Jeonguk Kang

Sang-Jin Oh

Minsu Kim

Young-Ho Park

Dohan Kim

Dae-Jeong Kim

Changmin Lee

Sung-Joon Kim

Dawoon Jung

Namhyung Kim

Tae-Kyeong Ko

Sang Lyul Min

Deokho Seo

Seongnam Kwon

Daejeong Kim

Yongjun Yu

Taesung Jung

Ilguy Jung

Donghyun Song

Wooseop Kim

Taeseok Hwang

Sheayun Lee

Yang Seok Ki

Jihwan Kim

Kitae Park

Jin Soo Kim

Munif Farhan

Changkyu Seol

Chul Ju Lee

Jonghwa Kim

Myung Hyun Jo

Nam Wook Kang

Sucheol Lee

In Hwan Doh

Byungsuk Woo

Sangyong Lee

Jongyoung Lee

Byung-gook Kim

Jiseok Kang

Cheolmin Park

Su-Gon Kim

Hui-Chung Byun

Dongbin Park

Inyoung Kim

Yong-Goo Lee

Jaemin Lim

Jaeyu Seo

Disclosed is an operating method of a storage device, which includes detecting virus/malware, performing an authentication operation with a host device when the virus/malware is detected, and entering a recovery mode when the authentication operation indicates that authentication is successful.

Storage device and method for protecting against virus/malware thereof and computing system having the same

Provided are an accelerator controlling a memory device, a computing system including the accelerator, and an operating method of the accelerator. The accelerator includes: a signal control/monitoring circuit configured to detect an entry to a self-refresh mode of a memory device and an exit from the self-refresh mode based on monitoring a signal provided from a host; an accelerator logic configured to generate a first command/address signal and a first piece of data; and a selector configured to output the first command/address signal and the first piece of data to the memory device based on detection of the entry to the self-refresh mode, and output a second command/address signal and a second piece of data provided from the host, to the memory device, based on detection of the exit from the self-refresh mode.

Accelerator controlling memory device, computing system including accelerator, and operating method of accelerator

A high bandwidth memory system includes a motherboard; and a semiconductor package coupled to the motherboard. The semiconductor package includes a package substrate mounted on the motherboard and including signal lines providing a plurality of channels; a first semiconductor device mounted on the package substrate and including a first physical layer (PHY) circuit; and a second semiconductor device mounted on the package substrate and including a second PHY circuit. The first semiconductor device and the second semiconductor device exchange a data signal with each other through the plurality of channels, the data signal is a multilevel signal having M levels, where M is a natural number greater than 2, and the first PHY circuit compensates for distortion of the channels and performs digital signal processing to compensate for a mismatch between the channels.

High bandwidth memory system using multilevel signaling

Provided are a memory device skipping a refresh operation and an operating method thereof. The memory device includes a memory cell array including N rows; a refresh controller configured to control a refresh operation for the N rows of the memory cell array based on a refresh command; and an access information storage circuit including a plurality of registers configured to store flag information corresponding to each of the N rows, wherein a first value indicates rows that have been accessed, and a second value indicates rows that have not been accessed. The refresh controller is further configured to control whether the refresh operation is performed for a first row of the N rows at a refresh timing for the first row based on the flag information corresponding to the first row.

Memory device skipping refresh operation and operation method thereof

A memory system includes a nonvolatile memory module and a first controller configured to control the nonvolatile memory module. The nonvolatile memory module includes a volatile memory device, a nonvolatile memory device, and a second controller configured to control the volatile memory device and the nonvolatile memory device. The first controller may be configured to transmit a read request to the second controller. When, during a read operation according to the read request, normal data is not received from the nonvolatile memory device, the first controller may perform one or more retransmits of the read request to the second controller without a limitation on a number of times that the first controller performs the one or more retransmits of the read request.

Memory system including memory module, memory module, and operating method of memory module

A storage device includes a non-volatile memory including a plurality of memory blocks and a storage controller configured to control a read operation of the non-volatile memory. The storage controller receives power-off time information indicating a power-off time point at which the storage device is powered off, and power-on time information indicating a power-on time point at which the storage device is powered on, when the storage device is switched from a power-off state to a power-on state. The storage controller stores a power-off time stamp corresponding to the power-off time point and a power-on time stamp corresponding to the power-on time point in the non-volatile memory.

Storage controller and storage device including the same

A memory system includes a processor that includes cores and a memory controller, and a first semiconductor memory module that communicates with the memory controller. The cores receive a call to perform a first exception handling in response to detection of a first error when the memory controller reads first data from the first semiconductor memory module. A first monarchy core of the cores performs the first exception handling and the remaining cores of the cores return to remaining operations previously performed.

Memory systems and operating methods of memory systems

A method of operating a nonvolatile memory system including a memory device having a plurality of memory blocks includes selecting a source block among the plurality of memory blocks in the nonvolatile memory system, and performing a reclaim operation for the source block based on the number of program and erase cycles which have been performed on the source block.

Method of operation for a nonvolatile memory system and method of operating a memory controller

A sustained status accelerating method for a storage device includes: controlling the storage device to receive a sustained status command from the outside; and controlling the storage device to enter the sustained status using a sustained valid page count (SVPC) table in response to the sustained status command so that each of a plurality of blocks constituting the storage device has a value greater than a predetermined valid page count. The SVPC table includes a valid page count with respect to each of the blocks in the storage device.

Storage device and sustained status accelerating method thereof

A storage device may include a main storage part including one or more memories; and a controller configured to control an overall operation of the main storage part. The controller includes a filter manager configured to store data format information and a filtering condition provided from a host; one or more stream filters configured to search and project data stored in the one or more memories in parallel in response to a control of the filter manager to produce searched and projected data; and a merge filter configured to merge the searched and projected data of the one or more stream filters in response to the control of the filter manager.

Storage device and stream filtering method thereof

A storage device may include a main storage part including memories; and a controller configured to control an overall operation of the main storage part. The controller includes a filter manager configured to store data format information and a filtering condition provided from a host; stream filters configured to search and project data stored in the memories in parallel in response to a control of the filter manager to produce searched and projected data; and a merge filter configured to merge the searched and projected data of the stream filters in response to the control of the filter manager.

A method of operating a storage device includes; counting a number of fast cycles for the memory block when a program interval between two successive program operations directed to memory cells of the memory block is less than a minimal program interval, and/or when an erase interval between two successive erase operations directed to the memory block is less than a minimal erase interval, and selecting the memory block to be erased by an erase operation or selecting memory cells of the memory block to be programmed by a program operation in response to the counted number of fast cycles for the memory block.

Storage device, nonvolatile memory and method operating same

A memory system is provided with a processor, a main memory, and a flash memory. Performance of the memory system is improved through achievement of speed-up and high data reliability. The memory system includes a nonvolatile memory device and a controller configured to drive a control program to control the nonvolatile memory device. The control program executes a second access operation for the nonvolatile memory device even before a first access operation to the nonvolatile memory device is completed.

Memory system and method of accessing a semiconductor memory device

Growing community of inventors

Hwaseong-si, South Korea

Chanik Park