Samsung Electronics Co., Ltd.

Chanho Yoon

Younggeon Yoo

Wonseb Jeong

Yang Seok Ki

Sangoak Woo

Beomkyu Shin

Jungmin Seo

Bumseok Yu

Myungjune Jung

Youngjin Cho

Hong Rak Son

Jeongho Lee

Junjin Kong

Kyoung Lae Cho

Changkyu Seol

Hongrak Son

Dohoon Kim

Aron Baik

Pilsang Yoon

Geunyeong Yu

Jinwon Kim

WooSeong Cheong

Hee Hyun Nam

Hyeokjun Choe

Seok-Won Ahn

Younho Jeon

Jaehun Jang

Hyeonwu Kim

Ipoom Jeong

JeongHo Lee

Hee Chang Cho

Kyunghun Jang

Junghyun Hong

Eunsoll Chang

Daekyoung Kim

Youmin Ha

Keunchan Oh

Provided is a robot including: a body rotatable about a first shaft; a first drive wheel and a second drive wheel provided in the body to be rotatable about a second shaft that is perpendicular to the first shaft; at least one distance sensor provided on the second shaft; and a processor. The processor may acquire first distance information through the at least one distance sensor at each of a plurality of different points at which the body is located as the body moves; acquire second distance information through the at least one distance sensor in each of a plurality of different directions in which the body is directed as the body rotates; and acquire, based on the first distance information and the second distance information, acquire information about a location point of the robot on a map corresponding to a space in which the robot is located.

Robot and controlling method thereof

A storage device includes a nonvolatile memory device and a storage controller. The storage controller includes a multi-protocol host interface circuit that receives a first-type request including a first logical address from an external host and transmits/receives data corresponding to the first-type request with the external host by a block unit. Additionally, the multi-protocol host interface circuit receives a second-type request including a first physical address from the external host and transmits/receives data corresponding to the second-type request with the external host by a unit smaller than the block unit. A mapping cache manager manages an address translation table cache, sends an address translation request including the first physical address to the external host, and receives a response including mapping information corresponding to the first physical address from the external host.

Storage device, operation method of storage device, and storage system using the same

A robot is provided. The robot includes a driving part, a three dimensional (3D) depth sensor, a memory storing instructions, and a processor connected to the driving part, the 3D depth sensor, and the memory. The processor is configured to execute the instructions to acquire a depth image of a driving surface photographed by the 3D depth sensor while the robot is driving in a space, acquire, based on the acquired depth image, location information of a boundary area where tilt information of the driving surface is changed, acquire type information corresponding to an outside area of the boundary area based on the acquired location information of the boundary area and the changed tilt information, and control the driving part based on the acquired type information.

A memory device includes; a first memory of first type, a second memory of second type different from the first type, and a memory controller. The memory controller receives an access request and workload information related to work of an external processor, processes the access request using the workload information, and accesses at least one of the first memory and the second memory in response to the access request.

Storage system and method to perform workload associated with a host

A storage device includes a plurality of non-volatile memories; a volatile memory; a computing device configured to perform an operation on data provided by the plurality of non-volatile memories; and a storage controller including a resource manager configured to receive information about priority of tenants from a host, and to dynamically set resources of the plurality of non-volatile memories, the volatile memory, and the computing device based on the priority.

Storage device supporting multi-tenancy and operating method thereof

A stacked neuromorphic device includes a logic die including a control circuit and configured to communicate with a host, and core dies stacked on the logic die and connected to the logic die via through silicon vias (TSVs) extending through the core dies. The core dies include a neuromorphic core die including a synapse array connected to row lines and column lines. The synapse array includes synapses configured to store weights and perform a calculation based on the weights and input data. The weights are included in layers of a neural network system. And the control circuit provides the weights to the neuromorphic core die through the TSVs and controls data transmission by the neuromorphic core die.

Stacked neuromorphic devices and neuromorphic computing systems

A method of operating a controller which controls a nonvolatile memory device includes enabling a command latch enable signal, an address latch enable signal, and a write enable signal and transmitting multiple data signals including a command and an address to the nonvolatile memory device in synchronization with the enabled write enable signal. A number of DQ lines through which the plurality of data signals are transmitted is greater than a number of bits of each of the data signals. The method also include disabling the command latch enable signal after the command is transmitted, and disabling the address latch enable signal and the write enable signal after the address is transmitted.

Storage device having wide input/output and method of operating the same

A device includes a first bus, a second bus, a processor configured to communicate with a storage circuit through the first bus and to communicate with a debug host through the second bus and a control circuit configured to inhibit transfer of data from the second bus to the debug host while receiving authentication information from the debug host and to enable transfer of data from the second bus to the debug host responsive to authentication of the received authentication information. The control circuit may be configured to inhibit data transfer from the second bus to the debug host by causing dummy data to be transmitted to the debug host over a transmit channel between the device and the debug host.

Storage devices with secure debugging capability and methods of operating the same

A method of storing data in a storage media can include determining whether a size of data to be stored in the storage media satisfies a reference condition and compressing the data to provide compressed data for storage in the storage media upon determining that the size satisfies a reference condition.

Method, device and system for storing data in storage media using a reference condition

A memory controller includes first and second interface controllers configured to exchange data with external devices, and an internal block connected between the first and second interface controllers. The first and second interface controllers exchange data received from the external devices and at least one parity bit corresponding to the received data through the internal block.

Memory controller and memory system including the same having interface controllers generating parity bits

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Seoul, South Korea

Chanho Yoon