Samsung Electronics Co., Ltd.

Chanho Lee

Hyunsoo Chung

Inyoung Lee

Hansung Ryu

Won-young Kim

Inhak Lee

Jinchan Ahn

Kyuwon Choi

Myeong Soon Park

Taehyung Kim

Won Tae Kim

Ae-Nee Jang

Sungdong Cho

Taemin Choi

JaeSeung Choi

Jung-Hak Song

Suk Youn

Sangyeop Baeck

Haeseok Park

Jinkuk Bae

Hyeongcheol Kim

Ingyu Park

Junghak Song

Juchang Lee

Ilgeun Jung

A static random access memory includes a memory cell that stores data, a reference voltage generator that generates a reference voltage, a precharge circuit that is connected with the memory cell through a bit line, is connected with the reference voltage generator through a reference bit line, and pre-charges the bit line and the reference bit line, and a sense amplifier that is connected with the bit line and the reference bit line, compares a voltage of the bit line and a voltage of the reference bit line to generate a comparison result, and determines a value of the data stored in the memory cell based on the comparison result. The reference voltage generator includes first-type transistors.

SRAM including reference voltage generator and read method thereof

A semiconductor device includes a substrate including a first memory cell, a second memory cell adjacent to the first memory cell in a first direction, and a comparator circuit adjacent to the first and second memory cells in a second direction intersecting the first direction; a true bit line and a complementary bit line electrically connected to the first and second memory cells and extending in the first direction from a first wiring layer on the substrate; a first power supply wiring on the first wiring layer, extending in the first direction between the true bit line and the complementary bit line and electrically connected to the first and second memory cells; first and second word lines extending in the second direction from a second wiring layer on the substrate different from the first wiring layer; first word line pads on the first wiring layer and electrically connecting the first memory cell to the first word line; second word line pads on the first wiring layer and electrically connecting the second memory cell to the second word line; and a first ground pad on the first wiring layer, electrically connected to the first and second memory cells, and in a same position as one of the first word line pads and one of the second word line pads in the second direction.

Semiconductor device

A semiconductor memory device includes a memory cell array that includes memory cells arranged in rows and columns, a row decoder that is configured to receive a row address, decode the row address, and adjust voltages of selection lines based on the decoded row address, a word line driver that is connected with the selection lines, is connected with the rows of the memory cells through word lines, and is configured to adjust voltages of the word lines in response to an internal clock signal and the voltages of the selection lines, and a detection circuit that is connected with the word lines and is configured to activate a detection signal in response to voltages of the word lines being identical at a specific timing.

Semiconductor memory devices

A semiconductor package may include a base, a first chip on the base, and first connection patterns that connect and couple the base and the first chip. The first chip may include a substrate, pad patterns on the substrate, a passivation layer on the substrate and having openings, and pillars on the substrate, the pad patterns include a first signal pad and a second signal pad, the first connection patterns are in contact with the pillars, the pillars include a first signal pillar in contact with the first signal pad and a second signal pillar in contact with the second signal pad, the openings in the passivation layer include a first opening having a sidewall facing a side surface of the first signal pillar and surrounding the side surface of the first signal pillar, and a second opening having a sidewall facing a side surface of the second signal pillar and surrounding the side surface of the second signal pillar, and a maximum width of the second opening is greater than a maximum width of the first opening.

Semiconductor packages

A semiconductor device including a substrate, an insulating layer on the substrate and including a trench, at least one via structure penetrating the substrate and protruding above a bottom surface of the trench, and a conductive structure surrounding the at least one via structure in the trench may be provided.

Semiconductor device and method for manufacturing the same

A memory device having fault detection functionality for improving functional safety and a control system including the memory device are provided. The memory device includes a first memory cell array configured to store input data and output the input data as output data and a second memory cell array configured to store bit values of a row address and a column address of the first memory cell array in which the input data is stored, and output the bit values of the row address and the column address as an internal row address and an internal column address. The row/column address designating a read operation may be compared to the internal row/column address, and an address comparison signal as a result of the comparison may be output. The address comparison signal may provide fault detection functionality for a data error of an automotive electronic system.

Memory device having fault detection functionality and control system including the same

Provided are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a metal line layer on a semiconductor substrate, and a metal terminal on the metal line layer. The metal line layer includes metal lines, and a passivation layer having a non-planarized top surface including flat surfaces on the metal lines and a concave surface between the metal lines. The metal terminal is provided on the passivation layer. Opposite lateral surfaces of the metal terminal facing each other are provided on the flat surfaces of the passivation layer.

Semiconductor device having metal bump and method of manufacturing the same

A semiconductor device including a substrate, an insulating, layer on the substrate and including a trench, at least one via structure penetrating the substrate and protruding above a bottom surface of the trench, and a conductive structure surrounding the at least one via structure in the trench may be provided.

A static random access memory device includes a plurality of memory cells arranged in rows and columns, a write driver configured to apply a bit line voltage corresponding to write data to a bit line extending in a column direction of the plurality of memory cells in a write operation, and a sub power line configured to transmit a cell driving voltage to the plurality of memory cells in the write operation and to extend in a direction parallel to the bit line, and includes a first node and a second node. The cell driving voltage is applied to the first node of the sub power line and the first node of the sub power line is aligned with an output node of the write driver in a row direction of the plurality of memory cells.

Static random access memory device having uniform write characteristics

A semiconductor device comprising: a substrate; a decoupling capacitor disposed on the substrate; a first connection pad vertically overlapping with the decoupling capacitor; a passivation layer exposing a portion of the first connection pad; and a first solder bump disposed on the first connection pad and covering a portion of a top surface of the passivation layer.

Semiconductor devices with redistribution pads are disclosed. The semiconductor device includes a plurality of electric pads provided on a semiconductor substrate, and a plurality of redistribution pads electrically connected to the electric pads and an outer terminal. The plurality of redistribution pads includes a plurality of first redistribution pads constituting a transmission path for a first electrical signal and at least one second redistribution pad constituting a transmission path for a second electrical signal different from the first electrical signal. The first redistribution pads are arranged on the semiconductor substrate to form at least two rows, and the at least one second redistribution pad is disposed between the at least two rows of the first redistribution pads.

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Hwaseong-si, South Korea

Chanho Lee