Freescale Semiconductor,inc.

Cadence Design Systems, Inc.

Chanhee Oh

David Theodore Blaauw

Vladimir P Zolotov

Rajendran Panda

Rafi Levy

Supamas Sirichotiyakul

John F Croix

Curtis L Ratzlaff

Abhijit Dharchoudhury

Murat R Becer

Amir Grinshpon

Ilan Algor

Timothy J Edwards

Judah L Adelman

Ramon D Acosta

David Moshe

In one embodiment, a method comprises creating a simulation model for a column of bit cells in a memory, simulating the simulation model to generate a result; and displaying the result for a user. Each of the bit cells in the column is coupled to a different wordline, and the simulation model comprises one or more linear elements in place of a nonlinear element in each bit cell that is coupled to an inactive wordline. The one or more linear elements approximate a behavior of the nonlinear element while the wordline is inactive. A computer accessible storage medium storing a simulator that implements the method is contemplated, and the simulator itself is also contemplated, in various embodiments.

High speed memory simulation

Processes and systems () for reducing pessimism in cross talk noise aware static timing analysis and thus resulting false path failures use either or both of effective delta delay noise () and path based delay noise () analysis. Effective delta delay determines an impact () on victim timing of an action by aggressors that occur during a region () where victim and aggressor timing windows overlap and determines an effective delta delaycorresponding to any portionof the impact on victim timing that extends beyond the victim timing window. The effective delta delay is used to adjust the victim timing window. Path based delta delay determines an uncertainty () in a switching time corresponding to a particular path for a victim resulting from an action (switching) by aggressors that occurs at the switching time, i.e. during a switching time window (ato a+u) () when uncertainty is included.

Pessimism reduction in crosstalk noise aware static timing analysis

A method of improving performance of a dual Vintegrated circuit is disclosed in which a first value is calculated for each transistor of the integrated circuit that has a first threshold voltage level. The first value is based at least in part on delay and leakage of the circuit calculated as if the corresponding transistor had a second threshold voltage level. One transistor is then selected based on the first values. The threshold voltage of the selected transistor is then set to the second threshold voltage level. The area of at least one transistor within the circuit is modified, and the circuit is then sized to a predetermined area. The process may then be repeated if the circuit performance fails to meet a defined constraint. In one embodiment, the performance determination includes calculating the leakage current of a set of DC-connected components into which the circuit is partitioned, determining dominant logic states for each of the components, estimating the leakage of each of these dominant logic states, and summing the weighted averages of these dominant components based on state probabilities.

Methods for analyzing integrated circuits and apparatus therefor

A solution to perform cross coupling delay characterization for integrated circuits and other microprocessor applications. The invention properly models the integrated circuit in various configurations at various times to accommodate the non-linearities associated with driver circuitry and the undesirable capacitive coupling between nets within the integrated circuit, specifically those that are located within close proximity to one another and that generate deleterious effects of the transitions of the drivers from low to high, and from high to low. The invention provides for a computationally efficient solution to perform the delay characterization of the speeding up and slowing down of individual transition operations within the microprocessor. Accurate delay characterization provides for design engineers an accurate description of the worst case and best case scenarios of the integrated circuit or microprocessor that is needed for various applications such as the integration of the integrated circuit and microprocessor into a larger system.

Cross coupling delay characterization for integrated circuits

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Austin, TX, United States of America

Chanhee Oh