Hrl Laboratories, LLC

Teledyne Scientific and Imaging, LLC

Chanh Nguyen

David H Chow

Joel N Schulman

Nguyen X Nguyen

Paul B Hashimoto

Daniel P Docter

Hooman Kazemi

Kenneth Robert Elliott

Berinder Brar

The disclosure relates to a zero-bias heterojunction diode detector with varying impedance. The detector includes a substrate supporting a Schottky structure and an Ohmic contact layer. A metallic contact layer is formed over the Ohmic layer. The Schottky structure comprises a plurality of barrier layers and each of the plurality of barriers layers includes a first material and a second material. In one embodiment, the composition percentage of the second material in each of the barrier layers increases among the plurality of barrier layers from the substrate to the metal layer in order to provide a graded periodicity for the Schottky structure.

Method and apparatus for heterojunction barrier diode detector for ultrahigh sensitivity

A process for fabricating ohmic contacts in a field-effect transistor includes the steps of: thinning a semiconductor layer forming recessed portions in the semiconductor layer; depositing ohmic contact over the recessed portions; and heating the deposited ohmic contacts. The field-effect transistor comprises a layered semiconductor structure which includes a first group III nitride compound semiconductor layer doped with a charge carrier, and a second group III nitride compound semiconductor layer positioned below the first layer, to generate an electron gas in the structure. After the heating step the ohmic contacts communicate with the electron gas. As a result, an excellent ohmic contact to the channel of the transistor is obtained.

Process for fabricating ultra-low contact resistances in GaN-based devices

A semiconductor device exhibiting interband tunneling with a first layer with a first conduction band edge with an energy above a first valence band edge, with the difference a first band-gap. A second layer with second conduction band edge with an energy above a second valence band edge, with the difference a second band-gap, and the second layer formed permitting electron carrier tunneling transport. The second layer is between the first and a third layer, with the difference between the third valence band edge and the third conduction band edge a third band-gap. A Fermi level is nearer the first conduction band edge than the first valence band edge. The second valence band edge is beneath the first conduction band edge. The second conduction band edge is above the third valence band edge. The Fermi level is nearer the third valence band edge than to the third conduction band edge.

Type II interband heterostructure backward diodes

A heterojunction bipolar transistor is presented, comprising a substrate having formed thereon a heterojunction bipolar transistor layer structure, and including an emitter layer. The emitter layer includes a strained, n-doped compound of indium arsenic and phosphorus. The transistor further comprises, between the substrate and emitter layer, a subcollector layer, a collector layer, a base layer, and an optional spacer layer. The emitter layer may include a graded portion. A contact layer is formed on the emitter layer to provide contacts for the device.

Low base-emitter voltage heterojunction bipolar transistor

Bipolar junction transistor (BJT) devices, particularly heterojunction bipolar transistor (HBT) devices, and methods of making same are described. A combination of InPSb and &rgr;-type InAs is used to create extremely high speed bipolar devices which, due to reduced turn-on voltages, lend themselves to circuits having drastically reduced power dissipation. The described HBTs are fabricated on InAs or GaSb substrates, and include an InPSb emitter. The base includes In and As, in the form of InAs when on an InAs substrate, and as InAsSb when on a GaSb substrate. The collector may be the same as the base to form a single heterojunction bipolar transistor (SHBT) or may be the same as the emitter to form a double heterojunction bipolar transistor (DHBT). Heterojunctions preferably include a grading layer, which may be implemented by continuously changing the bulk material composition, or by forming a chirped superlattice of alternating materials. The grading layer preferably has delta doping planes near its ends to form an electrostatic gradient offsetting the quasi-electric field variation due to the changes in material composition, whereby effective conduction band offset may be substantially eliminated to facilitate speed, and valence band offset increased proportionally to enhance gain.

InPSb/InAs BJT device and method of making

The present invention provides a varactor diode for frequency multipliers at submillimeter wave frequencies and above. Functionally the new diode replaces the conventional heterostructure barrier varactor diode. Two important features of the antimony-based quantum well heterostructure barrier varactor are; first: an aluminum antimnide/aluminum-arsenic-antimnide heterostructure barrier and second: a bandgap-engineered, triangular quantum well cathode and anode.

Antimony-based heterostructure varactor diode with bandgap engineered quantum well electrodes

A backward diode including a heterostructure consisting of a first layer of InAs and second layer of GaSb or InGaSb with an interface layer consisting of an aluminum antimonide compound is presented. It is also disclosed that the presence of AlSb in the interface enhances the highly desirable characteristic of nonlinear current-voltage (I-V) curve near zero bias. The backward diode is useful in radio frequency detection and mixing. The interface layer may be one or more layers in thickness, and may also have a continuously graded AlGaSb layer with a varying Al concentration in order to enhance the nonlinear I-V curve characteristic near zero bias.

Bipolar junction transistor (BJT) devices, particularly heterojunction bipolar transistor (HBT) devices, and methods of making same are described. A combination of InPSb and p-type InAs is used to create extremely high speed bipolar devices which, due to reduced turn-on voltages, lend themselves to circuits having drastically reduced power dissipation. The described HBTs are fabricated on InAs or GaSb substrates, and include an InPSb emitter. The base includes In and As, in the form of InAs when on an InAs substrate, and as InAsSb when on a GaSb substrate. The collector may be the same as the base to form a single heterojunction bipolar transistor (SHBT) or may be the same as the emitter to form a double heterojunction bipolar transistor (DHBT). Heterojunctions preferably include a grading layer, which may be implemented by continuously changing the bulk material composition, or by forming a chirped superlattice of alternating materials. The grading layer preferably has delta doping planes near its ends to form an electrostatic gradient offsetting the quasi-electric field variation due to the changes in material composition, whereby effective conduction band offset may be substantially eliminated to facilitate speed, and valence band offset increased proportionally to enhance gain.

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Calabasas, CA, United States of America

Chanh Nguyen