Hughes Electronics Corporation

Hughes Aircraft Company

Chanh N Nguyen

Takyiu Liu

Mehran Matloubian

Minh V Le

Nguyen Xuan Nguyen

Michael G Case

William W Hooper

Robert G Wilson

A process is provided for fabricating MODFET's in group III nitride compound semiconductors. The process precedes isolation of the MODFET structure with the use of e-beam lithography to define very narrow (e.g., .about.0.25 micrometer) gates which enhance transistor microwave cut-off frequency. Because these compound semiconductors resist chemical etchants, isolation is accomplished by etching with reactive ions to form an isolation mesa having a vertical mesa sidewall. To improve breakdown, the mesa sidewall is covered with a passivation layer prior to deposition of a gate feed that contacts the gate. To reduce parasitic gate capacitance, the gate feed is spaced from a narrow edge of the transistor's two-dimensional electron gas.

Modulation-doped field-effect transistors and fabrication processes

The number of surface defects in semiconductor materials having a volatile species, particulary group-III nitride-based semiconductor devices, are reduced by first implanting species atoms into the semiconductor sample to fill some of the surface layer species vacancies created by growth and device fabrication processes, and then rapid thermal annealing the sample to repair broken bonds and crystalline defects and to move implanted species atoms from interstitial to substitutional sites. An optional third step deposits a dummy layer on the sample surface prior to implantation, making possible an implantation profile that places a higher density of species atoms in the surface layer than is attainable without the dummy layer and to inhibit species atoms from leaving the sample during high-temperature processing steps that follow.

Method for reducing surface layer defects in semiconductor materials

Epitaxial growth of a chirped superlattice with constant dopings is achieved with minimal growth interruption time. This is done by doping only one of the two compositions during growth of its layer. For example, in the growth of a plurality of alternating layers of InP and GaInAs to form the superlattice, either the InP layers are doped with an n-type dopant, such as silicon, or the GaInAs layers are doped with a p-type dopant, such as beryllium. Alternatively, InP can equally be doped p-type (with beryllium) and GaInAs can be doped n-type (with silicon). In either case, the doping scheme described herein is easily done during molecular beam epitaxial growth by opening and closing the shutter of the dopant (silicon or beryllium) source cell at the appropriate times. To the electrical carriers, the doping superlattice scheme of the present invention presents a uniform doping without any need to change the doping cell temperature. This in turn allows improved controllability and minimal interface contamination.

Effective constant doping in a graded compositional alloy

An epitaxial structure and method of manufacture for a field-effect transistor capable of high-speed low-noise microwave, submillimeterwave and millimeterwave applications. Preferably, the epitaxial structure includes a donor layer and/or buffer layer made from a semiconductor material having the formula AlP.sub.0.39+y Sb.sub.0.61-y.

Method of making high-speed, low-noise millimeterwave HEMT and

An epitaxial structure and method of manufacture for a field-effect transistor capable of low-noise and power applications. Preferably, the epitaxial structure includes an N-type barrier layer comprising a wide-gap semiconductor material having the formula Al.sub.1-y Ga.sub.y P.sub.0.71+z Sb.sub.0.29-z.

Low-noise and power ALGaPSb/GaInAs HEMTs and pseudomorpohic HEMTs on

An epitaxial structure and method of manufacture for a single heterojunction bipolar transistor capable of being utilized in high-speed and high-power applications. Preferably, the epitaxial structure comprises an N-type collector made from InP, a P-type base made from InP, and an N-type emitter made from a semiconductor material of approximately 39 mole percent AlP and approximately 61 mole percent Sb.

AlPSb/InP single heterojunction bipolar transistor on InP substrate for

Method of making an AlPSb/InP single heterojunction bipolar transistor

A high-voltage bipolar transistor and fabrication method that comprises a shield electrode (or field-termination electrode) located between bond pads and underlying semiconductor material. The shield electrode is sandwiched between two isolating dielectric layers. High-voltage applied to the bond pad establishes an electric field between the bond pad and the shield electrode), preventing field penetration into and inversion of the underlying semiconductor material. Using this overlapping field-termination structure, low leakage current and high breakdown voltage is maintained in the transistor. The present overlapping field-termination structure provides an effective field termination underneath the bond pads, and because of its overlapping design, provides for a more compact transistor.

High-voltage bipolar transistor utilizing field-terminated bond-pad

A double heterojunction bipolar transistor (DHBT) is provided with a parabolic grade in bandgap at the base-collector junction. The parabolic grade in bandgap is close to parabolic in composition. The parabolic grade in bandgap is achieved by employing a chirped superlattice to mimic the parabolically varying alloy composition. Each period of the superlattice consists of one low-bandgap layer and one high-bandgap layer. The average composition in each period is determined by the relative thicknesses of these two layers. By varying the thickness ratio of these two layers approximately parabolically with (i) the distance from the base for a concave parabola and (ii) the distance from the collector for a convex parabola, the intended parabolic grade is achieved. The exact values may be computed numerically.

Growing community of inventors

Newbury Park, CA, United States of America

Chanh N Nguyen