Samsung Electronics Co., Ltd.

Sejong University

Changyup Park

Jeonghee Park

Dongho Ahn

Jiho Park

Jaeho Jung

Wonjun Park

Donggeon Gu

Jinwoo Lee

Kwangmin Park

Kyoung Sun Kim

Young-Lim Park

Hyunjae Song

Won-Jun Lee

Doyoon Kim

Hanjin Lim

Zhe Wu

Yumin Kim

Myunghun Woo

Kongsoo Lee

Chungman Kim

Jooheon Kang

Wook-Yeol Yi

WonSeok Yoo

Kwonyoung Kim

Hyokyoung Kim

Sukhwan Chung

Hwasung Chae

Suseong Noh

Yewon Kim

Okhyeon Kim

A method of forming a germanium antimony tellurium (GeSbTe) layer includes forming a germanium antimony (GeSb) layer by repeatedly performing a GeSb supercycle; and forming the GeSbTe layer by performing a tellurization operation on the GeSb layer, wherein the GeSb supercycle includes performing at least one GeSb cycle; and performing at least one Sb cycle, the GeSbTe has a composition of GeSbTe, in which a and b satisfy the following relations: −0.2<a<0.2 and −0.5<b<0.5.

Method of forming germanium antimony tellurium film

A semiconductor device includes a lower structure, a stack structure including gate layers and interlayer insulating layers alternately stacked on the lower structure in a first direction, and a channel structure in a channel hole passing through the stack structure. The channel structure includes a variable resistance material layer in the channel hole, a data storage material layer between the variable resistance material layer and a sidewall of the channel hole, and a channel layer between the data storage material layer and the sidewall of the channel hole, the channel layer includes a first element, the variable resistance material layer includes a second element, different from the first element, oxygen, and oxygen vacancies, and the data storage material layer includes the first element, the second element, oxygen, and oxygen vacancies.

Semiconductor devices and data storage systems including the same

A semiconductor device includes gate electrodes on a substrate, a channel and a resistance pattern. The gate electrodes are spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate. The channel extends through the gate electrodes in the vertical direction on the substrate. The resistance pattern includes a phase-changeable material. The resistance pattern includes a first vertical extension portion on a sidewall of the channel and extending in the vertical direction, a first protrusion portion on an inner sidewall of the first vertical extension portion and protruding in a horizontal direction substantially parallel to the upper surface of the substrate, and a second protrusion portion on an outer sidewall of the first vertical extension portion and protruding in the horizontal direction and not overlapping the first protrusion portion in the horizontal direction.

Semiconductor devices

A variable resistance memory device includes a first conductive line extending on a substrate in a first horizontal direction; a second conductive line extending on the first conductive line in a second horizontal direction perpendicular to the first horizontal direction; and a memory cell at an intersection between the first conductive line and the second conductive line, the memory cell including a selection element and a variable resistor, wherein the variable resistor includes a first variable resistance layer having a senary component represented by CGeSbTeAX, in which A and X are each a group 13 element different from each other, and 1≤a≤18, 13≤b≤26, 15≤c≤30, 35≤d≤55, 0.1≤e≤8, 0.1≤f≤8, and a+b+c+d+e+f=100.

Variable resistance memory device

An apparatus of fabricating a semiconductor device may include a chamber including a housing and a slit valve used to open or close a portion of the housing, a heater chuck provided in a lower region of the housing and used to heat a substrate, a target provided over the heater chuck, a plasma electrode provided in an upper region of the housing and used to generate plasma on the target, a heat-dissipation shield surrounding the inner wall of the housing between the plasma electrode and the heater chuck, and an edge heating structure provided between the heat-dissipation shield and the inner wall of the housing and configured to heat the heat-dissipation shield and an edge region of the substrate and to reduce a difference in temperature between center and edge regions of the substrate.

Apparatus for and method of fabricating semiconductor device

A semiconductor device includes a substrate; first conductive lines extending in a first direction; second conductive lines extending in a second direction; memory cell structures between the first conductive lines and the second conductive lines; and dummy cell structures that are electrically isolated and between the first conductive lines and the second conductive lines. The memory cell structures include a data storage material pattern including a phase change material layer; and a selector material pattern overlapping the data storage material pattern in a vertical direction. The dummy cell structures include a dummy pattern including a phase change material layer. The phase change material layer of the dummy pattern includes a crystalline phase portion and an amorphous phase portion. At a cross section of the phase change material layer of the dummy pattern, an area of the crystalline phase portion is larger than an area of the amorphous phase portion.

Semiconductor device including data storage material pattern

A method of fabricating a variable resistance memory device includes: forming a bottom electrode on a substrate; forming a dielectric layer on the substrate, wherein the dielectric layer has a first trench that exposes the bottom electrode; forming a variable resistance layer in the first trench; and irradiating the variable resistance layer with a laser, wherein the variable resistance layer is irradiated by the laser for a time of about 1.8 &#x3bc;s to about 54 &#x3bc;s.

Method of fabricating a variable resistance memory device

A variable resistance memory device including insulating patterns sequentially stacked on a substrate; first conductive lines between adjacent ones of the insulating patterns and spaced apart from each other in a first direction; a second conductive line between the first conductive lines and penetrating the insulating patterns in a third direction perpendicular to a top surface of the substrate; a phase-change pattern between the second conductive line and each of the first conductive lines and between the adjacent ones of the insulating patterns to cover a top surface of a first adjacent insulating pattern and a bottom surface of a second adjacent insulating pattern; and a selection element between the phase-change pattern and the second conductive line and between the adjacent ones of the insulating patterns to cover the top surface of the first adjacent insulating pattern and the bottom surface of the second adjacent insulating pattern.

Disclosed are a collimator, a fabrication apparatus including the same, and a method of fabricating a semiconductor device using the same. The fabrication apparatus may include a chamber, a heater chuck provided in a lower region of the chamber and configured to heat a substrate, a target provided over the heater chuck, the target containing a source for a thin layer to be deposited on the substrate, a plasma electrode provided in an upper region of the chamber and configured to generate plasma near the target and thereby to produce particles from the source, and a collimator provided between the heater chuck and the target.

Collimator, fabrication apparatus including the same, and method of fabricating a semiconductor device using the same

A variable resistance memory device may include insulating layers stacked on a substrate, a first conductive line penetrating the insulating layers, switching patterns between the insulating layers, a phase change pattern between the first conductive line and each of the switching patterns, and a capping pattern disposed between the phase change pattern and the first conductive line and disposed in a region surrounded by the phase change pattern.

Variable resistance memory devices and methods of manufacturing variable resistance memory devices

Apparatus for and method of fabricating semiconductor devices

Disclosed is a method of fabricating a semiconductor device. The method may include forming a mold layer on a substrate, the mold layer having a hole exposing a portion of the substrate, forming a phase transition layer with a void, in the hole, and thermally treating the phase transition layer to remove the void from the phase transition layer. The thermal treating of the phase transition layer may include heating the substrate to a first temperature to form a diffusion layer in the phase transition layer, and the first temperature may be lower than or equal to 55% of a melting point of the phase transition layer.

Method of fabricating semiconductor devices

Provided is a method of forming a semiconductor device. The method can include loading a semiconductor substrate into semiconductor equipment. A base layer can be formed on the loaded semiconductor substrate by performing a base deposition process using a base source material. A first silicon layer can be formed on the base layer to a greater thickness than the base layer by performing a first silicon deposition process using a silicon source material different from the base source material. A first nitrided silicon layer can be formed by nitriding the first silicon layer using a first nitridation process. The semiconductor substrate having the first nitrided silicon layer can be unloaded from the semiconductor equipment.

Growing community of inventors

Hwaseong-si, South Korea

Changyup Park