Lsi Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Agere Systems Inc.

Changyou Xu

Shaohua Yang

Yang Han

Zongwang Li

Kiran Kumar Gunnam

Weijun Tan

Yuan Xing Lee

Hao Zhong

Kapil Gaba

Chung-Li Wang

Richard Rauschmayer

Fan Zhang

Wu Chang

Harley Burger

Ching-Fu Wu

Erich Franz Haratsch

Wei Zhang

Ming Jin

Timothy Lawrence Canepa

Lei Chen

Nils Graef

Kelly K Fitzpatrick

Yang Liu

Jefferson E Singleton

Nital P Patwa

Madhusudan Kalluri

David G Springberg

Sancar Kunt Olcay

Kaichi Zhang

Kurt J Worrell

Kripa Venkatachalam

Chien Chen

Zhi Kai Chen

Jonseung Park

Chung-Li Yang

Haitoa Xia

Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit, a data decoder circuit, and a gating circuit.

Systems and methods for governing power usage in an iterative decoding system

The present invention is a programmable QC LDPC encoder for encoding user data. The encoder may be configurable for implementation with a read channel. The encoder may include a plurality of barrel shifter circuits. The barrel shifter circuits are configured for generating a plurality of parity bits based on interleaved user bits received by the encoder. The barrel shifter circuits are further configured for outputting the parity bits. The encoder may further include an encoder interleaver memory. The encoder interleaver memory may be communicatively coupled with the barrel shifter circuits and may receive the parity bits output from the barrel shifter circuits. The encoder interleaver may be configured for interleaving the parity bits. Further, the encoder may be configured for outputting the interleaved parity bits to a multiplexer. The barrel shifter circuits may generate the plurality of parity bits via an encoding algorithm: p=u*G.

Programmable quasi-cyclic low-density parity check (QC LDPC) encoder for read channel

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for power governance in a data processing system. In one particular case, a system is disclosed that includes a first data processing circuit operable to apply a data detection algorithm to a data input synchronous to a first clock, and a second data processing circuit operable to apply a subsequent data processing algorithm to an output derived from the first data processing circuit synchronous to a second clock, and an idle time enforcement circuit operable to modify an average frequency of at least one of the first clock and the second clock.

Systems and methods for idle clock insertion based power control

Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a combination data decoder circuit. The combination data decoder circuit includes: a non-binary data decoder circuit and a binary data decoder circuit.

Systems and methods for combined binary and non-binary data processing

Hardware-based methods and apparatus are provided for inter-track interference mitigation in magnetic recording systems. Inter-track interference (ITI) is mitigated in a magnetic recording system by obtaining ITI cancellation data; and providing the ITI cancellation data to an ITI mitigation circuit using a write data path in the magnetic recording system. The write data path can optionally operate substantially simultaneously with the read data path performing the read operation. The ITI cancellation data comprises, for example, user data and/or media data.

Hardware-based methods and apparatus for inter-track interference mitigation in magnetic recording systems

Various embodiments of the present invention provide systems and methods for data processing. Such data processing includes data shuffling.

Systems and methods for efficient data shuffling in a data processing system

Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes: a data detector circuit, a pseudo-random sequence generator circuit, a decoder circuit, and a pseudo-random sequence reconstitution circuit. The data detector circuit is operable to apply a data detection algorithm to a first data set to yield a detected output. The pseudo-random sequence generator circuit is operable to generate an interim data sequence and to generate a second data set based upon a combination of the detected output and the interim data sequence. The decoder circuit is operable to apply a data decode algorithm to a derivative of the second data set to yield a third data set.

Systems and methods for efficient data channel testing

A method for processing a read sub-command in a secondary storage controller is disclosed. The method includes receiving the read sub-command from a primary storage controller; retrieving data in response to the read sub-command; utilizing a write request to write the retrieved data directly to a memory accessible by a host device; issuing an additional request to the same memory after the write request; receiving an indication of completion of the additional request; and reporting a sub-completion status to the primary storage controller.

Method to ensure data coherency in a scalable aggregate neighbor-device interface

Various embodiments of the present invention provide systems and methods for decoding of non-binary LDPC codes. For example, a low density parity check data decoder is disclosed that includes a variable node processor operable to perform variable node updates based at least in part on check node to variable node message vectors, a check node processor operable to perform check node updates and to generate the check node to variable node message vectors, and a scheduler operable to cause the variable node processor to use check node to variable node message vectors from multiple decoding iterations when performing the variable node updates for a given decoding iteration.

Non-binary LDPC decoder with low latency scheduling

Various embodiments of the present inventions are related to adaptive calibration of NPFIR filters in a data detector. For example, an apparatus for calibrating a noise predictive filter is disclosed, including a data detector operable to generate detected values for data sectors and having an embedded noise predictive finite impulse response filter. The apparatus also includes a comparator operable to determine whether a quality metric for a current one of the data sectors meets a noise threshold. The apparatus also includes a filter calibration circuit operable to adapt a number of filter coefficients for the noise predictive finite impulse response filter based on the detected values for the data sectors, and to omit the detected values for the current one of the data sectors from adaptation for one of the filter coefficients if the quality metric for the current one of the data sectors does not meet the noise threshold.

Adaptive calibration of noise predictive finite impulse response filter

In one embodiment, a turbo equalizer has an LDPC decoder, a channel detector, and one or more adjustment blocks for recovering an LDPC codeword from a set of input samples. The decoder attempts to recover the codeword from an initial set of channel soft-output values and generates a set of extrinsic soft-output values, each corresponding to a bit of the codeword. If the decoder converges on a trapping set, then the channel detector performs detection on the set of input samples to generate a set of updated channel soft-output values, using the extrinsic soft-output values to improve the detection. The one or more adjustment blocks adjust at least one of (i) the extrinsic soft-output values before the channel detection and (ii) the updated channel soft-output values. Subsequent decoding is then performed on the updated and possibly-adjusted channel soft-output values to attempt to recover the codeword.

Adjusting soft-output values in turbo equalization schemes to break trapping sets

Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a read circuit and a combining circuit. The read circuit is operable to provide a first instance of a user data set, a second instance of the user data set, and a third instance of the user data set. The combining circuit is operable to: combine at least a first segment of the first instance of the user data set with a first segment of the second instance of the user data set to yield a first combined data segment; provide a second combined data set that includes a combination of one or more second segments from the second instance of the user data set and the third instance of the user data set; and provide an aggregate data set including at least the first combined data set and the second combined data set. The second combined data set does not incorporate a second segment of the first instance of the user data set.

Systems and methods for sample averaging in data processing

Various embodiments of the present invention provide systems and methods for monitoring out of order data decoding. For example, a method for monitoring out of order data processing is provided that includes receiving a plurality of data sets that is associated with a plurality of identifiers with each of the plurality of identifiers indicates a respective one of the plurality of data sets; storing each of the plurality of identifiers in a FIFO memory in an order that the corresponding data sets of the plurality of data sets was received; processing the plurality of data sets such that at least one of the plurality of data sets is provided as an output data set; accessing the next available identifier from the FIFO memory; and asserting an out of order signal when the next available identifier is not the same as the identifier associated with the output data set.

Systems and methods for monitoring out of order data decoding

In one embodiment, a turbo equalizer has a channel detector that receives equalized samples and generates channel soft-output values. An LDPC decoder attempts to decode the channel soft-output values to recover an LDPC-encoded codeword. If the decoder converges on a trapping set, then an adjustment block selects one or more of the equalized samples based on one or more specified conditions and adjusts the selected equalized samples. Selection may be performed by identifying the locations of unsatisfied check nodes of the last local decoder iteration and selecting the equalized samples that correspond to bit nodes of the LDPC-encoded codeword that are connected to the unsatisfied check nodes. Adjustment of the equalized samples may be performed using any combination of scaling, offsetting, and saturation. Channel detection is then performed using the adjusted equalized samples to generate an updated set of channel soft-output values, which are subsequently decoded by the decoder.

Adjusting input samples in turbo equalization schemes to break trapping sets

In a communications system that demultiplexes user data words into multiple sub-words for encoding and decoding within different subword-processing paths, the minimum distance between bit errors in an extrinsic codeword can be increased by having corresponding subword encoders/decoders in the different subword-processing paths perform subword encoding/decoding with different encoder/decoder matrices.

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Fremont, CA, United States of America

Changyou Xu