Samsung Electronics Co., Ltd.

Changyong Um

JungChak Ahn

Youngnam Hwang

Jeongjin Lee

Byungjun Park

Youngwoo Jung

An image sensor may include a device isolation structure defining a plurality of pixel regions in a substrate and a photoelectric conversion element formed in each of the pixel regions. The device isolation structure may include an insulating gapfill layer extending from an upper portion to a lower portion of the device isolation structure, a spacer provided at the upper portion of the device isolation structure and interposed between the insulating gapfill layer and the substrate, and a lower impurity region provided at the lower portion of the device isolation structure and interposed between the insulating gapfill layer and the substrate.

Image sensors

An image sensor includes a substrate with a unit pixel defined by a first separation pattern, a photoelectric conversion part in the substrate, a photocharge storage in the substrate, the photocharge storage being adjacent to the photoelectric conversion part, a second separation pattern between the photoelectric conversion part and the photocharge storage, a shielding part on a bottom surface of the substrate to cover the photocharge storage, the shielding part including a first protrusion extending into the substrate and toward the first separation pattern, and an extension extending from the first protrusion to cover the bottom surface of the substrate; and an anti-reflection layer between the shielding part and the substrate, the anti-reflection layer having an overhang structure between the first protrusion and the extension.

Image sensor

A variable resistance memory device includes; a memory cell array comprising a plurality of memory cells, a pulse shifter shifting a plurality of program pulses to generate a plurality of shifted program pulses, a write and verification driver receiving the plurality of shifted program pulses to provide a program current that varies with the plurality of shifted program pulses to the plurality of memory cells, and control logic providing the plurality of program pulses to the pulse shifter and the write and verification driver during a program/verification operation, such at least two write data bits are programmed to the memory cell array in parallel during the program/verification operation.

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Seoul, South Korea

Changyong Um