Shenzhen China Star Optoelectronics Technology Co., Ltd.

Changyeh Lee

Xiaojiang Yu

Tzuchieh Lai

Shangcao Cao

Shengdong Zhang

Wenying Li

Congwei Liao

Zhijin Hu

Limei Zeng

The present invention provides a CMOS gate driving circuit, comprising a plurality of shift register units which are cascade connected, and the shift register unit of the nth stage comprises: a forward-backward scan module, a latch module () electrically coupled to the forward-backward scan module and an output module () electrically coupled to the latch module; the forward-backward scan module comprises: a first module () and a second module (), and the first module () is a transmission module in forward scan and a pull-down module in backward scan; the second module () is a pull-down module in forward scan and a transmission module in backward scan; both the first module () and the second module () comprise a NAND gate, which can achieve forward-backward scan for ensuring the stability of the GOA function and the smooth output of the scan voltage signal to raise the stage transfer efficiency and to effectively reduce the sequence delay of the stage transfer; meanwhile, the multiple functions of the circuit module can be achieved, and the frame width of the screen can be decreased and the power consumption can be lowered.

CMOS gate driving circuit

The present invention relates to a GOA circuit for tablet display and a display device. The GOA circuit comprises cascaded plurality of GOA units, the GOA unit comprises a pull-up control partand a transfer part; the transfer partcomprises a first thin film transistor T, the gate thereof is connected with the gate signal point Q(n), the drain and the source are respectively input the clock signal CK(n) and output the turn-on signal ST(n); the pull-up control part comprises: a second thin film transistor T, the gate thereof is input the turn-on signal ST(n&#x2212;2), the drain and the source are respectively connected with the horizontal scan line G(n&#x2212;2) and the gate signal point Q(n); a third tin film transistor T, the gate thereof is connected with the horizontal scan line G(n&#x2212;1), the drain and the source are respectively connected with the horizontal scan line G(n&#x2212;1) and the gate signal point Q(n). The present invention also provides a related display device. The present invention can improve the stability of the GOA circuit and the related display device in high temperature.

GOA circuit for tablet display and display device

The present invention relates to a GOA circuit for liquid crystal displaying and a display device. The GOA circuit includes a plurality of cascaded GOA units and the nth-stage GOA unit includes a pull-up part (), a key pull-down part (), a pull-down holding part (), a pull-up control part (), and a boost capacitor (Cb). In operation, a nth-stage clock signal (CK(n)) and first and second clock signals (LCand LC) are inputted. The frequencies of the first clock signal (LC) and the second clock signal (LC) are lower than the nth clock signal (CK(n)). The first clock signal (LC) charging a first circuit point (P) and the second clock signal (LC) charging a second circuit point (K) are alternately carried out. The present invention also provides a corresponding display device. The GOA circuit of the present invention precisely controls the voltage of the gate Q(n) that affects charging of a horizontal scan line by means of the low frequency clock signal and the high frequency clock signal, so as to ensure a stable output of the GOA charging signal.

GOA circuit for liquid crystal displaying and display device

The present invention provides a gate driver on array (GOA) circuit and a display panel with the GOA circuit. The driver circuit includes multiple stages of gate driver units and multiple stages of supplementary gate driver units connected in cascade, in which the nth stage gate driver unit includes a driving unit () and a pull-down unit () and the mth stage supplementary gate driver unit includes a supplementary driving unit () and a supplementary pull-down unit (). The GOA circuit according to the present invention adopts a dual-pull-down architecture so that thin-film transistors contained in pull-down units and supplementary pull-down units of the circuit can be set in an operation environment featuring dual polarity electrical biasing to effectively suppress threshold voltage drifting of the thin-film transistors of the pull-down units and the supplementary pull-down units and extend the lifespan of circuit thereby making the circuit better meet the needs of large- and medium-sized display panels. Further, the circuit has a simple structure and reduced power consumption and is also fit to low temperature and high temperature operations.

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Shenzhen, China

Changyeh Lee