Samsung Electronics Co., Ltd.

Seoul National University

Changwook Jeong

In Huh

Sanghoon Myung

Jisu Ryu

Min-Chul Park

Jeonghoon Ko

Hyunjae Jang

Hyojin Choi

Younsik Park

Hyeon Kyun Noh

Seungju Kim

Wonik Jang

Hyungtae Kim

Jinwoo Kim

Taehoon Kim

Jun Haeng Lee

Yohan Kim

Jongwon Kim

Yongwoo Lee

Hyunjoong Kim

Sunghee Lee

Yongwoo Jeon

Youngmin Oh

Jaeho Jeong

Moon Hyun Cha

Hyun Sun Park

Jaecheol Lee

Kanghyun Baek

Il Chae Jung

Moonhyun Cha

Jaepil Shin

Younggu Kim

Jaemyung Choe

Bo Hyung Han

Yunrong Li

Daeyoung Park

Min Chul Jeon

Joonwan Chai

Yejin Jeong

Ami Ma

A method of clustering patterns of an integrated circuit includes; providing a pattern image and numeric data, as input data corresponding to a first pattern to a first model, wherein the first model is trained by a plurality of sample images and a plurality of sample values, obtaining a content latent variable using the first model, and grouping a plurality of content latent variables corresponding to a plurality of patterns into a plurality of clusters based on a Euclidean distance, wherein the numeric data represents at least one attribute of the first pattern.

Method and system performing pattern clustering

An object tracking learning system includes a first neural network module that expresses and learns a first parameter for an input image from a first type to a second type and outputs the learned result as a first learning result, a second neural network module that removes and learns a connection of a part of a second parameter for the input image and outputs the learned result as a second learning result, a prediction module that generates a prediction value for an object of the input image from a summation result obtained by summing the first learning result and the second learning result, and an optimization module that updates the first parameter and the second parameter based on the prediction value.

Learning method and system for object tracking based on hybrid neural network

A method of generating a circuit model used to simulate an integrated circuit may include generating first feature element data and second feature element data by classifying feature data of a target semiconductor device according to measurement conditions, generating first target data and second target data by preprocessing the first feature element data and the second feature element data, respectively, generating a first machine learning model using the first target data and extracting a second machine learning model using the second target data, and generating the circuit model used to simulate the integrated circuit using the first machine learning model and the second machine learning model.

Methods of generating circuit models and manufacturing integrated circuits using the same

A system verification method includes generating a first verification vector as a result of a first action of an agent, the first verification vector referring to an observation corresponding to at least one state already covered, from among states of elements of a target system, identifying a first coverage corresponding to at least one state covered by the first verification vector, from among the states of the elements, updating the observation by reflecting the first coverage in the observation, and generating a second verification vector through a second action of the agent, the second verification vector referring to the updated observation.

Method and apparatus with system verification based on reinforcement learning

According to an aspect of the present inventive concept, a simulation method for a semiconductor fabrication process includes obtaining, as input data, process parameters for controlling a semiconductor process of manufacturing semiconductor devices, or design parameters representing a structure of the semiconductor devices, or both the process parameters and the design parameters; generating predictive data for electrical characteristics of the semiconductor devices using a machine learning model based on the input data; generating reference data for the electrical characteristics of the semiconductor devices using a simulation tool based on the input data; and training the machine learning model using the predictive data and the reference data.

Simulation method for semiconductor fabrication process and method for manufacturing semiconductor device

Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.

Simulation system for semiconductor process and simulation method thereof

A system for modeling a semiconductor fabrication process includes at least one first processor and at least one second processor. The at least one first processor is configured to provide at least one machine learning (ML) model, which is trained by using a plurality of pairs of images of a design pattern sample and a physical pattern sample. The physical pattern sample is formed from the design pattern sample by using the semiconductor fabrication process. The at least one second processor is configured to provide an input image representing a shape of a design pattern and/or a physical pattern to the at least one first processor and to generate output data defining the physical pattern and/or the design pattern based on an output image received from the at least one first processor.

System and method for modeling a semiconductor fabrication process

A non-transitory computer-readable medium storing a program code including an image generation model, which when executed, causes a processor to input input data including sampling data of some of a plurality of semiconductor dies of a wafer to a generator network of the image generation model and output a wafer map indicating the plurality of semiconductor dies, and to input the wafer map output from the generator network to a discriminator network of the image generation model and discriminate the wafer map.

Non-transitory computer-readable medium storing program code generating wafer map based on generative adversarial networks and computing device including the same

A semiconductor wafer fault analysis system includes: a database to store a first reference map, which is classified as a first fault type, and a second reference map, which is classified as a second fault type; a first auto-encoder/decoder to remove a noise corresponding to the first fault type from the first reference map to generate a first pre-processed reference map; a second auto-encoder/decoder to remove a noise corresponding to the second fault type from the second reference map to generate a second pre-processed reference map; and a fault type analyzer. The database is updated based on the first and second pre-processed reference maps, and the fault type analyzer is to classify a fault type of a target map based on the updated database. The target map is generated by measuring a target wafer.

Semiconductor wafer fault analysis system and operation method thereof

A proximity correction method for a semiconductor manufacturing process includes: generating a plurality of pieces of original image data from a plurality of sample regions, with the sample regions selected from layout data used in the semiconductor manufacturing process; removing some pieces of original image data that overlap with each other from the plurality of pieces of original image data, resulting in a plurality of pieces of input image data; inputting the plurality of pieces of input image data to a machine learning model; obtaining a prediction value of critical dimensions of target patterns included in the plurality of pieces of input image data from the machine learning model; measuring a result value for critical dimensions of actual patterns corresponding to the target patterns on a semiconductor substrate on which the semiconductor manufacturing process is performed; and performing learning of the machine learning model using the prediction value and the result value.

Proximity correction methods for semiconductor manufacturing processes

An electronic device configured to generate a verification vector for verifying a semiconductor circuit including a first circuit block and a second circuit block includes a duplicate command eliminator configured to receive a first input vector including a plurality of commands and to provide a first converted vector, in which ones of the plurality of commands that generate the same state transition are changed into idle commands, based on a state transition of the first circuit block obtained by performing a simulation operation on the first input vector, a reduced vector generator configured to provide a first reduced vector in which a number of repetitions of the idle commands included in the first converted vector is reduced, and a verification vector generator configured to output the first reduced vector having a coverage that coincides with a target coverage among a plurality of first reduced vectors as a first verification vector.

Electronic devices generating verification vector for verifying semiconductor circuit and methods of operating the same

A fault analysis method of a semiconductor fault analysis device is provided. The fault analysis method includes: receiving measurement data measured corresponding to a semiconductor device; generating double sampling data based on the measurement data and reference data; performing a fault analysis operation with respect to the double sampling data; classifying a fault type of the semiconductor device based on a result of the fault analysis operation; and outputting information about the fault type.

Semiconductor fault analysis device and fault analysis method thereof

Growing community of inventors

Hwaseong-si, South Korea

Changwook Jeong