Intel Corporation

Changwon D Rhee

Joydeep Ray

Wajdi K Feghali

Hong Jiang

Ben J Ashbaugh

Sang-Hee Lee

Zhijun Lei

Alexander Lyashevsky

Timothy R Bauer

Supratim Pal

Kin-Hang W Cheung

Jason Daniel Tanner

Changliang Wang

Yong Jiang

Lei Chen

Wei-Yu Chen

Fangwen Fu

Ning Lu

Yunbiao Lin

Bo Zhao

Jian Zhou

Tiehan Lu

Li Xu

Ping Liu

Dmitry E Ryzhov

Wei Xiong

Jiasheng Chen

Li-An Tang

Naiqian Lu

Jay M Patel

Danyu Bi

Prathamesh Raghunath Shinde

Xiaodong Qiu

Xinglei Zhu

Gomathi Ramamurthy

Richard Gui Xie

Cui Tang

Saimanohara S Alapati

Shuangpeng Zhou

Peiqing Jiang

Chengxi Wu

Qingyuan Zhang

An apparatus to facilitate a fused instruction to accelerate performance of secure hash algorithm 2 (SHA-2) in a graphics environment is disclosed. The apparatus includes a processor comprising processing resources, the processing resources comprising execution circuitry to receive a fused SHA instruction identifying a length corresponding to a data size of the fused SHA instruction and a functional control identifying an operation type of the fused SHA instruction; based on decoding the fused SHA instruction, cause a sub-function identified by the length and the function control to be scheduled to an integer pipeline of the execution resource; and execute the sub-function of the fused SHA instruction in an integer pipeline of the execution circuitry, the sub-function to perform merged operations on a source operand of the fused SHA instruction, the merged operations comprising a rotate operation, a shift operation, and an xor operation.

Fused instruction to accelerate performance of secure hash algorithm 2 (SHA-2) workloads in a graphics environment

An apparatus to facilitate large integer multiplication enhancements in a graphics environment is disclosed. The apparatus includes a processor comprising processing resources, the processing resources comprising multiplier circuitry to: receive operands for a multiplication operation, wherein the multiplication operation is part of a chain of multiplication operations for a large integer multiplication; and issue a multiply and add (MAD) instruction for the multiplication operation utilizing at least one of a double precision multiplier or a 48 bit output, wherein the MAD instruction to generate an output in a single clock cycle of the processor.

Large integer multiplication enhancements for graphics environment

Embodiments are generally directed to methods and apparatuses for dynamically changing data priority in a cache. An embodiment of an apparatus comprising: a priority controller to: receive a memory access request to request data; and set a priority flag for the memory access request based on an accumulated access amount of data stored in a memory block to be accessed by the memory access request to dynamically change a priority level of the requested data.

Methods and apparatuses for dynamically changing data priority in a cache

Independent workloads may be grouped together into a single super workload. This super workload is dispatched to a single context hardware system that does not run an operating system. This effectively creates a multi-context system out of a single context hardware processor.

Enabling a single context hardware system to operate as a multi-context system

Methods, systems and computer program products that may improve the efficiency of the video encoding process. Mode decision processing and bit stream packing may be performed in parallel for various frames in a sequence. This reduces the amount of idle time for both the mode decision processing logic and the bit stream packing logic, improving the overall efficiency of the video encoder.

Systems, methods, and computer program products for a video encoding pipeline

Techniques related to compositing video content are discussed. Such techniques may include generating transparency data for a surface of first video content and storing it in a stream out buffer, accessing the transparency data via the stream out buffer when there is no change to the surface of the first video content, and compositing the first video content with second video content based on the accessed transparency data.

Low power video composition using a stream out buffer

Various embodiments are generally directed to an apparatus, method and other techniques for dividing a frame comprising pixels into a number of macroblocks, each macroblock comprising a number of pixels within four macroblock boundaries. Various embodiments may also include creating at least two regions having a plurality of macroblocks by dividing the frame along macroblock boundaries and generating wave front groups based on the macroblocks in each region, each wave front group from each region comprising one or more macroblocks to process in parallel.

Techniques for generating wave front groups for parallel processing a video frame by a video encoder

A method of pitch corrected speed control (PCSC) playback in which a decoder rate controller receives a desired playback speed from a PCSC controller and determines the number of decoded digital audio samples stored in a buffer. The rate controller then determines the required number of execution times of a parametric speech decoder based on the desired playback speed and the number of decoded samples stored in the buffer. The parametric speech decoder is then executed the determined number of times.

Speed control playback of parametric speech encoded digital audio

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Rocklin, CA, United States of America

Changwon D Rhee