Samsung Electronics Co., Ltd.

Changsup Mun

Kyunghyun Kim

Sanghoon Jeong

Sunil Shim

Sangjun Hong

Taeheon Kim

Seungcheol Chae

Junyoul Yang

Yongsik Chung

A wet etching method includes: providing a structure including an etching target film into a process bath containing a first etching solution having a first phosphoric acid concentration; performing a first etching process for etching the etching target film with the first etching solution in the process bath; providing a second etching solution having a second phosphoric acid concentration different from the first phosphoric acid concentration by changing a phosphoric acid concentration in the first etching solution; performing a second etching process for etching the etching target film with the second etching solution in the process bath; providing a third etching solution having a third phosphoric acid concentration different from the first and second phosphoric acid concentrations by changing a phosphoric acid concentration in the second etching solution; and performing a third etching process for etching the etching target film with the third etching solution in the process bath.

Wet etching method and method of fabricating semiconductor device by using the same

A semiconductor memory device includes a stack structure comprising horizontal electrodes sequentially stacked on a substrate including a cell array region and an extension region and horizontal insulating layers between the horizontal electrodes. The semiconductor memory device may further include vertical structures that penetrate the stack structure, a first one of the vertical structures being on the cell array region and a second one of the vertical structures being on the extension region. Each of the vertical structures includes a channel layer, and a tunneling insulating layer, a charge storage layer and a blocking insulating layer which are sequentially stacked on a sidewall of the channel layer. The charge storage layer of the first vertical structure includes charge storage patterns spaced apart from each other in a direction perpendicular to a top surface of the substrate with the horizontal insulating layers interposed therebetween. The charge storage layer of the second vertical structure extends along sidewalls of the horizontal electrodes and sidewalls of the horizontal insulating layers.

Semiconductor memory device and method of manufacturing the same

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Hwaseong-si, South Korea

Changsup Mun