Freescale Semiconductor,inc.

Nxp Usa, Inc.

Changsoo Hong

Chai Ean Gill

Rouying Zhan

Patrice Besse

James D Whitfield

Amaury Gendron

Michael H Kaneshiro

William G Cowden

Jean Philippe Laine

Jean-Philippe Laine

Jean-Phillippe Laine

An area-efficient, low voltage ESD protection device () is provided for protecting low voltage pins () against ESD events by using one or more stacked low voltage NPN bipolar junction transistors, each formed in a p-type material with an N+ collector region () and P+ base region () formed on opposite sides of an N+ emitter region () with separate halo extension regions (-) formed around at least the collector and emitter regions to improve the second trigger or breakdown current (It) and set the snapback voltage (Vsb) and triggering voltage (Vt) at the desired level.

Low voltage NPN with low trigger voltage and high snap back voltage for ESD protection

An electrostatic discharge protection device includes a buried layer having a plurality of heavily doped regions of a first conductivity type and a laterally diffused region between adjacent heavily doped regions, a semiconductor region over the buried layer, and a first well of the first conductivity type extending from a surface of the semiconductor region to a heavily doped region. The device includes a first transistor in the semiconductor region having an emitter coupled to the first terminal, and a second transistor in the semiconductor region having an emitter coupled to the second terminal. The first well forms a collector of the first transistor and a collector of the second transistor.

ESD protection device

An ESD protection structure formed within a semiconductor substrate of an integrated circuit device. The ESD protection structure comprises a thyristor structure being formed from a first P-doped section forming an anode of the thyristor structure, a first N-doped section forming a collector node of the thyristor structure, a second P-doped section, and a second N-doped section forming a cathode of the thyristor structure. A low-resistance coupling is provided between an upper surface region of the collector node of the thyristor structure and the anode of the thyristor structure.

ESD protection structure

An electrostatic protection includes a buried layer having an outer region and an inner region which are heavily doped regions of a first conductivity type. The inner region is surrounded by an undoped or lightly doped ring region. The ring region is surrounded by the outer region. The device further includes a semiconductor region over the buried layer, a first well of the first conductivity type in the semiconductor region, a first transistor in the semiconductor region, and a second transistor in the semiconductor region. The first well forms a collector of the first transistor and a collector of the second transistor.

An ESD protection device is fabricated in a semiconductor substrate that includes a semiconductor layer having a first conductivity type. A first well implantation procedure implants dopant of a second conductivity type in the semiconductor layer to form inner and outer sinker regions. The inner sinker region is configured to establish a common collector region of first and second bipolar transistor devices. A second well implantation procedure implants dopant of the first conductivity type in the semiconductor layer to form respective base regions of the first and second bipolar transistor devices. Conduction of the first bipolar transistor device is triggered by breakdown between the inner sinker region and the base region of the first bipolar transistor device. Conduction of the second bipolar transistor device is triggered by breakdown between the outer sinker region and the base region of the second bipolar transistor device.

ESD protection with asymmetrical bipolar-based device

An electrostatic discharge (ESD) protection device includes a semiconductor substrate, a base region in the semiconductor substrate and having a first conductivity type, an emitter region in the base region and having a second conductivity type, a collector region in the semiconductor substrate, spaced from the base region, and having the second conductivity type, a breakdown trigger region having the second conductivity type, disposed laterally between the base region and the collector region to define a junction across which breakdown occurs to trigger the ESD protection device to shunt ESD discharge current, and a gate structure supported by the semiconductor substrate over the breakdown trigger region and electrically tied to the base region and the emitter region. The lateral width of the breakdown trigger region is configured to establish a voltage level at which the breakdown occurs.

ESD protection with integrated LDMOS triggering junction

An electrostatic discharge (ESD) protection device includes a semiconductor substrate comprising a buried insulator layer and a semiconductor layer over the buried insulator layer having a first conductivity type, and first and second bipolar transistor devices disposed in the semiconductor layer, laterally spaced from one another, and sharing a common collector region having a second conductivity type. The first and second bipolar transistor devices are configured in an asymmetrical arrangement in which the second bipolar transistor device includes a buried doped layer having the second conductivity type and extending along the buried insulator layer from the common collector region across a device area of the second bipolar transistor device.

An electrostatic discharge (ESD) protection clamp () for protecting associated devices or circuits (), comprises a bipolar transistors () in which doping of facing base () and collector () regions is arranged so that avalanche breakdown occurs preferentially within a portion () of the base region () of the device () away from the overlying dielectric-semiconductor interface (). Maximum variations (&#x394;Vt)of ESD triggering voltage Vtas a function of base-collector spacing dimensions D due, for example, to different azimuthal orientations of transistors () on a semiconductor die or wafer is much reduced. Triggering voltage consistency and manufacturing yield are improved.

ESD protection device and method

Protection device structures and related fabrication methods are provided. An exemplary protection device includes a first bipolar junction transistor, a second bipolar junction transistor, a first zener diode, and a second zener diode. The collectors of the first bipolar junction transistors are electrically coupled. A cathode of the first zener diode is coupled to the collector of the first bipolar transistor and an anode of the first zener diode is coupled to the base of the first bipolar transistor. A cathode of the second zener diode is coupled to the collector of the second bipolar transistor and an anode of the second zener diode is coupled to the base of the second bipolar transistor. In exemplary embodiments, the base and emitter of the first bipolar transistor are coupled at a first interface and the base and emitter of the second bipolar transistor are coupled at a second interface.

Protection device and related fabrication methods

An electrostatic discharge protection clamp adapted to limit a voltage appearing across protected terminals of an integrated circuit to which the electrostatic discharge protection clamp is coupled is presented. The electrostatic discharge protection clamp includes a substrate, and a first electrostatic discharge protection device formed over the substrate. The first electrostatic discharge protection device includes a buried layer formed over the substrate, the buried layer having a first conductivity type and defining an opening located over a region of the substrate, a first transistor formed over the opening of the buried layer, the first transistor having an emitter coupled to a first cathode terminal of the electrostatic discharge protection clamp, and a second transistor formed over the buried layer, the second transistor having an emitter coupled to a first anode terminal of the electrostatic discharge protection clamp.

Electrostatic discharge (ESD) protection clamps for I/O terminals of integrated circuit (IC) cores comprise a bipolar transistor with an integrated Zener diode coupled between the base and collector of the transistor. Variations in clamp voltage in different parts of the same IC chip or wafer caused by conventional deep implant geometric mask shadowing are avoided by using shallow implants and forming the base coupled anode and collector coupled cathode of the Zener using opposed edges of a single relatively thin mask. The anode and cathode are self-aligned, and the width of the Zener space charge region between them is defined by the opposed edges substantially independent of location and orientation of the ESD clamps on the die or wafer. Because the mask is relatively thin and the anode and cathode implants relatively shallow, mask shadowing is negligible and prior art clamp voltage variations are avoided.

Devices with zener triggered ESD protection

Electrostatic discharge (ESD) protection clamps () for I/O terminals () of integrated circuit (IC) cores () comprise a bipolar transistor () with an integrated Zener diode () coupled between the base () and collector () of the transistor (). Prior art variations () in clamp voltage in different parts of the same IC chip or wafer caused by prior art deep implant geometric mask shadowing are avoided by using shallow implants () and forming the base () coupled anode () and collector () coupled cathode () of the Zener () using opposed edges () of a single relatively thin mask (). The anode () and cathode () are self-aligned and the width () of the Zener space charge region () therebetween is defined by the opposed edges () substantially independent of location and orientation of the ESD clamps () on the die or wafer. Because the mask () is relatively thin and the anode () and cathode () implants () relatively shallow, mask shadowing is negligible and prior art clamp voltage variations () are avoided.

Zener triggered ESD protection

An improved lateral bipolar electrostatic discharge (ESD) protection device () comprises a semiconductor (SC) substrate (), an overlying epitaxial SC layer (), emitter-collector regions () laterally spaced apart by a first distance () in the SC layer, a base region () adjacent the emitter region () extending laterally toward and separated from the collector region () by a base-collector spacing () that is selected to set the desired trigger voltage Vt. By providing a buried layer region () under the emitter region () Ohmically coupled thereto, but not providing a comparable buried layer region () under the collector region (), an asymmetrical structure is obtained in which the DC trigger voltage (Vt) and transient trigger voltage (Vt) are closely matched so that |Vt&#x2212;Vt|&#x2dc;0. This close matching increases the design margin and provides a higher performance ESD device () that is less sensitive to process variations, thereby improving manufacturing yield and reducing cost.

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Phoenix, AZ, United States of America

Changsoo Hong