Samsung Electronics Co., Ltd.

ChangSik Yoo

Kihan Kim

Yonghun Kim

Junghwan Choi

Youngdon Choi

Jaewoo Lee

Youngchul Cho

Hojun Yoon

Hyochang Kim

Jaewoo Jeong

Yongun Jeong

Donghyeok Jeong

A semiconductor device includes: a data clock signal generator circuit configured to output a plurality of data clock signals that have different phases and that are used to generate a plurality of internal data clock signals of a memory device; a data transmitter configured to generate a data signal based on a test pattern transitioned once, delay the data signal once transitioned according to a delay value, and output the data signal to the memory device; a data receiver configured to receive an output signal from the memory device that includes first sampling data, the first sampling data being obtained by sampling the data signal based on a first internal data clock signal from the plurality of internal data clock signals; and a training circuit configured to change the delay value and determine a final value of the delay value based on the first sampling data.

Semiconductor device

A memory device includes a DC conversion circuit that receives a first edge-triggered phase signal having first pulses each extending from a rising edge of a first phase signal of a multiphase clock to a later rising edge of a second phase signal of the multiphase clock and a second edge-triggered phase signal having second pulses each extending from a rising edge of the second phase signal to a later rising edge of the first phase signal, and outputting a first voltage corresponding to the first edge-triggered phase signal and a second voltage corresponding to the second edge-triggered phase signal, a comparator that compares the first voltage with the second voltage, control logic that generates a control code corresponding to an output value from the comparator, and a delay cell that delays the second phase signal according to the control code.

Memory device, system and method employing multiphase clock

A memory device includes a multi-phase clock generator configured to generate first to N-th clock signals having N different phases based on a clock signal from the memory controller, and a monitoring clock signal generator configured to generate a monitoring clock signal having a logic state corresponding to a data pattern in synchronization with edges of the first to N-th clock signals, wherein the monitoring clock signal includes a first monitoring clock signal configured to detect a skew between the first and third clock signals in a first step of a training operation, a second monitoring clock signal configured to detect a skew between the second and fourth clock signals in a second step of the training operation, and a third monitoring clock signal configured to detect a skew between the first and second clock signals in a third step of the training operation.

Memory device adjusting skew of multi-phase clock signals, memory controller controlling the memory device, and operating method of the memory device

A semiconductor device includes: a clock generation circuit configured to output a plurality of clock signals that have different phases to a memory device, an internal clock signal of the memory device being generated responsive to the plurality of clock signals; and a training circuit configured to receive an output signal output based on the internal clock signal from the memory device, to adjust a value of a code used to generate the internal clock signal by adjusting the phase of at least one clock signal among the plurality of clock signals, to determine a final value of the code based on a duty cycle of the output signal, which is changed according to the adjustment of the value of the code, and to write the final value to the memory device.

Disclosed is a clock multiplexing circuit which includes a first transistor that is between a first input terminal that receives a first input clock signal and an output terminal that outputs an output pulse signal and operates based on a logic level of a second input terminal receiving a second input clock signal, and a second transistor that is between the output terminal and a first voltage node and operates based on the logic level of the second input terminal. The first input clock signal and the second input clock signal have the same period and have different phases. The output pulse signal transitions to a first logic level at a first time when the first input clock signal transitions to the first logic level and transitions to a second logic level at a second time when the second input clock signal transitions to the first logic level.

Clock multiplexing circuit

A semiconductor memory device includes a quadrature error correction circuit, a clock generation circuit and a data input/output (I/O) buffer. The quadrature error correction circuit performs a locking operation to generate a first corrected clock signal and a second corrected clock signal by adjusting a skew and a duty error of a first through fourth clock signals generated based on a data clock signal and performs a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal. The clock generation circuit generates an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal. The data I/O buffer generates a data signal by sampling data from a memory cell array based on the output clock signal and transmits the data signal and the strobe signal to a memory controller.

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Suwon-si, South Korea

ChangSik Yoo