Samsung Electronics Co., Ltd.

Industry-university Cooperation Foundation Hanyang University

Skhynix Inc.

Samsung Electro-mechanics Co., Ltd.

University of Seoul Industry Cooperation Foundation

Iucf-hyu (industry-university Cooperation Four

Changsik Yoo

Junghwan Choi

Youngdon Choi

Yonghun Kim

Jaemin Choi

Yoochang Sung

Kyungmin Kim

Jaewoo Park

Kyongho Kim

Jaewoo Jeong

Keun-Seon Ahn

Jangwoo Lee

Jung Chul Gong

Jeongdon Ihm

Kyungryun Kim

Jae Shin Lee

Yu Jin Jang

Joong Ho Choi

Youngchul Cho

Chul Bum Kim

Young Jin Moon

Yong Seong Roh

Kyoungho Kim

Hojun Yoon

Jeong Mo Yang

Hyunah An

Baekjin Lim

Jinhyeok Baek

Donghyeok Jeong

Jinho Noh

Chunseok Jeong

Jin-Gyu Kang

Minki Jeon

A semiconductor device includes: a plurality of pads connected to a memory device receiving a data signal using first to fourth clock signals having different phases; a data transmission/reception circuit inputting and outputting the data signal to a plurality of data pads of the plurality of pads and including a data delay cell adjusting a phase of the data signal; a clock output circuit outputting first to fourth clock signals to a plurality of clock pads of the plurality of pads and including first to fourth clock delay cells adjusting phases of the first to fourth clock signals; and a controller adjusting a delay amount of at least one of the first to fourth clock delay cells and the data delay cell so that each of the first to fourth clock signals is aligned with the data signal in the memory device.

Semiconductor device with adjustment of phase of data signal and clock signals, and memory system including the same

Disclosed is a transmitter which includes an encoder and a transmission interface circuit. The encoder receives data bits and generates conversion bits, a number of is the conversion bits being more than a number of the data bits, based on the number of the data bits. The encoder detects a risk pattern of the conversion bits to generate detection data and converts the risk pattern into a replacement pattern based on the detection data to generate code bits, a number of is the code bits being equal to the number of the conversion bits.

Transmitter transmitting signals to channels, receiver receiving signals from channels, and semiconductor system including the transmitter and the receiver

A memory device includes a first rank having first memory banks and a first quad skew adjustment circuit and a second rank having second memory banks and a second quad skew adjustment circuit, wherein each of the first quad skew adjustment circuit and the second quad skew adjustment circuit is configured to: receive a 4-phase clock through first channels; detect internal quad skew of the 4-phase clock; correct skew of the 4-phase clock according to the detected quad skew; and output mode register information corresponding to the detected quad skew through a second channel.

Memory devices, memory systems having the same, and operating methods thereof

An interface circuit includes: a buffer circuit configured to receive an input signal and to generate an output signal having a delay time, the delay time being determined based on a current level of a bias current and a voltage level of a power supply voltage; and a bias generation circuit configured to vary a voltage level of a bias control voltage so that the delay time is constant by compensating for a change in the voltage level of the power supply voltage, the bias generation circuit being further configured to provide the bias control voltage to the buffer circuit.

Interface circuit and operating method thereof to compensate for supply voltage variations

A semiconductor memory device includes a quadrature error correction circuit, a clock generation circuit and a data input/output (I/O) buffer. The quadrature error correction circuit performs a locking operation to generate a first corrected clock signal and a second corrected clock signal by adjusting a skew and a duty error of a first through fourth clock signals generated based on a data clock signal and performs a relocking operation to lock the second corrected clock signal to the first corrected clock signal in response to a relock signal. The clock generation circuit generates an output clock signal and a strobe signal based on the first corrected clock signal and the second corrected clock signal. The data I/O buffer generates a data signal by sampling data from a memory cell array based on the output clock signal and transmits the data signal and the strobe signal to a memory controller.

Semiconductor memory device and memory system including the same

Provided are a memory device and a memory system including the same. The memory device may include a data bus inversion (DBI) mode selector configured to select a first multi-bit DBI signal from among a plurality of multi-bit DBI signals respectively corresponding to a plurality of DBI modes according to multi-bit data; a multi-mode DBI encoder configured to generate encoded multi-bit data by DBI encoding the multi-bit data according to the first multi-bit DBI signal; and a transceiver configured to transmit a data symbol corresponding to the encoded multi-bit data through a data channel and transmit a DBI symbol corresponding to the first multi-bit DBI signal through a DBI channel.

Data processing device and memory system including the same

A serializer includes data input circuits configured to receive N-number of pieces of data in parallel, where N is an even number, data connection circuits configured to receive internal clock signals having different phases in different arrangements, and data output circuits configured to output the N-number of pieces of data in sequence in a single cycle of each of the internal clock signals, wherein the data connection circuits operate the data output circuits such that the data output circuits, in response to the internal clock signals, output corresponding data of the N-number of pieces of data in an enable period in the single cycle and have a high impedance state in a disable period in the single cycle.

Serializer and memory device including the same

A data transmitting and receiving system includes a first device including an encoder configured to encode row data to generate precoding data and a transmitter configured to transmit the precoding data through a transmission channel and a second device including an integrator configured to perform an integral on the precoding data, an integral sampler including a plurality of samplers configured to output sampling data based on an offset value and an output value of the integrator, a decoder configured to decode outputs of some of the samplers to generate decoded data, and a phase detector configured to detect a phase difference between the precoding data and a clock based on the decoded data and an output of another one of the samplers.

Data transmitting and receiving system including clock and data recovery device and operating method of the data transmitting and receiving system

A regulator includes a switch array, a feedback circuit, first and second voltage-controlled oscillators, and a switch driver. The switch array generates an output voltage based on a number of enabled switches from among a plurality of switches. The feedback circuit generates a feedback voltage which depends on a level of the output voltage. The first voltage-controlled oscillator generates a first signal having a first frequency which depends on a difference between a reference voltage and the feedback voltage. The second voltage-controlled oscillator generates a second signal having a second frequency which depends on a difference between the feedback voltage and the reference voltage. The switch driver determines a turn-on time point of each of the plurality of switches based on the first signal and determining a turn-off time point of each of the plurality of switches based on the second signal.

Regulator and operating method thereof

Memory device and memory system including the same

A semiconductor device includes a first data transmitting/receiving circuit, a second data transmitting/receiving circuit, and a plurality of channels configured to couple the first and second data transmitting/receiving circuits. The first data transmitting/receiving circuit includes a Tx delay unit configured to transmit data to the plurality of channels, an Rx delay unit configured to receive data from the plurality of channels, and a de-skew control unit configured to control delay amounts of the Tx delay unit and the Rx delay unit according to phase information of reference clock signals received through the plurality of channels.

Semiconductor device performing de-skew operation

An analog to digital converter is provided. The analog to digital converter includes: an arithmetic operator combining an analog input signal with a feedback signal; a loop filter filtering an output signal of the arithmetic operator; a quantizer quantizing an output signal of the loop filter to output a digital signal; and a feedback converting the digital signal to output a feedback signal, in which the quantizer includes: a plurality of VCOs each receiving a positive output signal and a negative output signal of the loop filter and outputting VCO signals; a plurality of samplers receiving the VCO signals output from the plurality of VCOs, respectively and outputting sampled signals; and a phase detector detecting a phase difference in the sampled signals output from the plurality of samplers, respectively, to detect a phase difference in two VCO signals output from the plurality of VCOs, respectively.

Analog to digital converter including differential VCO

A transmitter operates by receiving a first power supply voltage and a second power supply voltage lower than the first power supply voltage, and includes a driving circuit that generates an output signal according to a driving control signal, a swing adjustment block that adjusts a swing width of the output signal to be lower than a difference between the first power supply voltage and the second power supply voltage in response to a swing control signal, and a swing control signal generation circuit that generates the swing control signal based on the output signal.

Transmitter

A data transmitting and receiving apparatus includes a coil configured to transmit and receive data through inductive coupling, where a voltage drop across the coil constitutes a sensing signal. The apparatus further includes an input unit configured to generate transmission data and a replica signal in accordance with an input data signal, the transmission data being supplied to the coil. The apparatus still further includes a replica unit configured to generate a compensation signal in accordance with the replica signal, and an output unit configured to extract reception data from the sensing signal using the compensation signal.

Data transmitting and receiving apparatus and method, and solid state drive including the same

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Seoul, South Korea

Changsik Yoo