Anchor Semiconductor Inc.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Changsheng Ying

Ru-Gun Liu

Hsu-Ting Huang

Fu An Tien

A computer-implemented method includes executing, using a computer, a process including a main thread that receives a layout file. The layout file includes a first plurality of tags and compressed information blocks. Each tag of the first plurality is associated with a compressed information block. The method further includes decompressing the compressed information blocks using sub-threads and thereby obtaining decompressed information blocks. The sub-threads are created by the main thread, and each sub-thread corresponds to a compressed information block. The decompressed information blocks are combined into decompressed layout information. The decompressed file is partitioned and each partition is provided to a node of a distributed computing system for performing layout correction. Multiple result files each in a compressed format are obtained from the distributed computing system and the result files are combined to obtain a single result file without decompressing and re-compressing the results from the distributed computing system.

Importing and exporting circuit layouts

A method for applying optical proximity correction (OPC) to a circuit layout, includes storing distinct defect patterns in a defect pattern library and modifying the circuit layout to fix defect pattern. The method also includes storing a distinct patterns in an OPC pattern library storing one or more post-OPC targets in association with one of distinct patterns in the OPC pattern library, wherein the one or more post-OPC targets are configured to correct optical proximity effects of the associated distinct pattern. The method further includes identifying in the circuit layout a pattern that has substantially the same optical proximity environment as the one of the distinct patterns in the OPC pattern library; and applying OPC to the identified pattern using the one or more post-OPC targets associated with the one of the distinct pattern in the OPC pattern library.

Pattern match based optical proximity correction and verification of integrated circuit layout

A method of inspecting full-chip mask data to locate layout pattern design induced defects and weak points that cause functional failure or performance degradation for integrated circuits (ICs) manufactured in subwavelength technology. Given the pre-OPC integrated circuit design layout data, the method of present invention refers to available post-OPC data or generates post-OPC data condition to do the inspection based on the modeling of integrated circuit wafer patterning. Build-in direct checks of specified electrical functional defects and a multilayer pattern-centric approach are used to improve the accuracy and performance. A technique of adaptive search is used to speed up the critical dimension search during the process of optical proximity correction data verification. A defect synthesis capability is supplied for defect disposition to facilitate systematic correction and prevention of the defects in integrated circuit layout design.

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San Jose, CA, United States of America

Changsheng Ying