Samsung Electronics Co., Ltd.

Ulsan National Institute of Science and Technology

Insprit Co., Ltd.

Seoul National University

Changseok Lee

Jonghyun Park

Hyeonjin Shin

Keunwook Shin

Kyung-Eun Byun

Hyunjae Song

Changhyun Kim

Yeonchoo Cho

Eunkyu Lee

Sangwon Kim

Hyeonsuk Shin

Seongjun Park

Seokmo Hong

Seunggeol Nam

Minhyun Lee

Alum Jung

Jaeho Lee

Minsu Seol

Yonghoon Kim

Taejin Choi

Kyungyeol Ma

Soyoung Lee

Jieun Kim

Hyangsook Lee

Jongyoub Ryu

Kyungeun Byun

Yunjae Lim

Hyunsuk Min

Junho Koh

Jaeeun Kang

Sangsun Choi

Sungjoo An

Yonghyun Lim

Seungwon Lee

Sangsoo Lee

Hyun Soo Park

Dongwook Lee

Seyun Kim

Janghee Lee

Hanjin Lim

Seongjun Jeong

Hyunseok Lim

Youngtek Oh

Jongmyeong Lee

Jeonil Lee

Changhoon Jung

Youngjun Choi

Dongjin Yun

Kibum Kim

Donghyun Im

Van Luan Nguyen

Kaoru Yamamoto

Taein Kim

Joongki Moon

Jungsoo Yoon

Junho Ko

Seongheon Kim

Hyuntae Hwang

Seongin Yoon

Byoungki You

An interconnect structure for reducing a contact resistance, an electronic device including the same, and a method of manufacturing the interconnect structure are provided. The interconnect structure includes a semiconductor layer including a first region having a doping concentration greater than a doping concentration of the rest region of the semiconductor layer, a metal layer facing the semiconductor layer, a semi-metal layer between the semiconductor layer and the metal layer, and a conductive metal oxide layer between the semi-metal layer and the semiconductor and covering the first region.

Interconnect structure to reduce contact resistance, electronic device including the same, and method of manufacturing the interconnect structure

Provided are nanocrystalline graphene and a method of forming the same. The nanocrystalline graphene may include a plurality of grains formed by stacking a plurality of graphene sheets and has a grain density of about 500 ea/μmor higher and a root-mean-square (RMS) roughness in a range of about 0.1 or more to about 1.0 or less. When the nanocrystalline graphene has a grain density and a RMS roughness with these ranges, nanocrystalline graphene capable of covering the entirety of a large area on a substrate as a thin layer may be provided.

Nanocrystalline graphene and method of forming nanocrystalline graphene

A vertical channel transistor includes a first source/drain electrode; a second source/drain electrode spaced apart from the first source/drain electrode in a first direction; a first channel pattern between the first source/drain electrode and the second source/drain electrode; a first gate electrode on a side surface of the first channel pattern; a first gate insulation layer between the first channel pattern and the first gate electrode; and a first graphene insertion layer between the first source/drain electrode and the first channel pattern.

Vertical channel transistor including a graphene insertion layer beweeen a source/drain electrode and a channel pattern

Provided are a wiring including a graphene layer and a method of manufacturing the wiring. The method may include growing a graphene layer on a substrate and doping the graphene layer with a metal. The graphene layer may be grown using a plasma of a hydrocarbon at a temperature of about 200° C. to about 600° C. by plasma enhanced chemical vapor deposition (PECVD).

Wiring including graphene layer and method of manufacturing the same

Provided is a thin film structure including a substrate, a metal layer on the substrate and spaced apart from the substrate, and a two-dimensional material layer between the substrate and the metal layer. The two-dimensional material layer may be configured to limit and/or block an electron transfer between the substrate and the metal layer. A resistivity of a metal layer on the two-dimensional material layer may be lowered by the two-dimensional material layer.

Thin film structure and electronic device including two-dimensional material

Provided is a vertical nonvolatile memory device in which a thickness of one memory cell is reduced to reduce an entire thickness of a memory cell string and increase the number of stacked memory cells. The nonvolatile memory device includes a plurality of memory cell strings. Each of the memory cell strings may include a plurality of insulating spacers each extending in a first direction, a plurality of gate electrodes each extending in the first direction and alternately arranged with the plurality of insulating spacers in a second direction perpendicular to the first direction, and a plurality of contacts respectively arranged to contact a side surface of the plurality of gate electrodes respectively corresponding to the plurality of contacts.

Vertical nonvolatile memory device including memory cell string

Provided are a vertical-channel cell array transistor structure and a dynamic random-access memory (DRAM) device including the same. The vertical-channel cell array transistor structure includes a semiconductor substrate, a plurality of channels arranged in an array on the semiconductor substrate and each extending perpendicularly from the semiconductor substrate, a gate insulating layer on the plurality of channels, a plurality of word lines on the semiconductor substrate and extending in a first direction, and a two-dimensional (2D) material layer on at least one surface of each of the plurality of word lines.

Vertical-channel cell array transistor structure and dram device including the same

Provided are a black phosphorus-two dimensional material complex and a method of manufacturing the black phosphorus-two dimensional material complex. The black phosphorus-two dimensional material complex includes: first and second two-dimensional material layers, which each have a two-dimensional crystal structure and are coupled to each other by van der Waals force; and a black phosphorus sheet which between the first and second two-dimensional material layers and having a two-dimensional crystal structure in which a plurality of phosphorus atoms are covalently bonded.

Black phosphorus-two dimensional material complex and method of manufacturing the same

A method of forming nanocrystalline graphene according to an embodiment may include: arranging a substrate having a pattern in a reaction chamber; injecting a reaction gas into the reaction chamber, where the reaction gas includes a carbon source gas, an inert gas, and a hydrogen gas that are mixed; generating a plasma of the reaction gas in the reaction chamber; and directly growing the nanocrystalline graphene on a surface of the pattern using the plasma of the reaction gas at a process temperature. The pattern may include a first material and the substrate may include a second material different from the first material.

Method of forming nanocrystalline graphene

A film deposition method may include preparing a non-planar substrate including a first surface, a second surface, and an inclined surface between the first surface and the second surface; depositing a film having a thickness deviation on the first surface, the second surface, and the inclined surface; and etching the film deposited on the first surface, the second surface, and the inclined surface. A height of the second surface may be different than a height of the first surface.

Film deposition method and element including film deposited by the film deposition method

An interconnect structure and an electronic apparatus including the interconnect structure are provided. The interconnect structure includes a conductive layer; a dielectric layer configured to surround at least a part of the conductive layer; and a diffusion barrier layer disposed between the conductive layer and the dielectric layer and configured to limit and/or prevent a conductive material of the conductive layer from diffusing into the dielectric layer, and at least one of the dielectric layer and the diffusion barrier layer includes a boron nitride layer of a low dielectric constant.

Interconnect structure and electronic apparatus including the same

Disclosed herein is a method of fabricating hexagonal boron nitride in which hexagonal boron nitride is epitaxially grown. A method of fabricating hexagonal boron nitride includes placing a catalytic metal in a chamber, the catalytic metal having a hexagonal crystal structure and having a lattice mismatch of 15% or less with hexagonal boron nitride (h-BN) in a chamber; and growing hexagonal boron nitride on the catalytic metal at a temperature of 800° C. or lower while supplying a nitrogen source and a boron source into the chamber.

Method of fabricating hexagonal boron nitride

A boron nitride layer and a method of fabricating the same are provided. The boron nitride layer includes a boron nitride compound and has a dielectric constant of about 2.5 or less at an operating frequency of 100 kHz.

Boron nitride layer, apparatus including the same, and method of fabricating the boron nitride layer

A graphene structure and a method of forming the graphene structure are provided. The graphene structure includes directly grown graphene that is directly grown on a surface of a substrate and has controlled surface energy.

Graphene structure and method of forming the graphene structure

A method of forming graphene includes: preparing a substrate in a reaction chamber; performing a first growth process of growing a plurality of graphene aggregates apart from each other on the substrate at a first growth rate by using a reaction gas including a carbon source; and performing a second growth process of forming a graphene layer by growing the plurality of graphene aggregates at a second growth rate slower than the first growth rate by using the reaction gas including the carbon source.

Method of forming graphene

Growing community of inventors

Seoul, South Korea

Changseok Lee