Intel Corporation

Sk Hynix Nand Product Solutions Corp.

Changpeng Liu

Ziye Yang

Gang Cao

Shaopeng He

Yadong Li

Xiaodong Liu

Cunming Liang

James R Harris

Anjali Singhai Jain

Daniel Daly

Jiang Yu

Ping Yu

Liang J Ma

Jingjing Wu

Bo Cui

Hongjun Ni

Benjamin Walker

Zhiguo Wen

Sanjeev N Trika

Piotr Wysocki

Jonathan M Hughes

Jackson Ellis

Haitao Kang

Qihua Dai

Gregory Tucker

Sujoy Sen

Robert O Sharp

Yi Zou

Scott David Peterson

Arun Raghunath

Chong Han

Vishal Verma

Banghao Ying

Cunyin Chang

Qun Wan

Examples described herein relate to receiving memory access requests in a first number of connections from one or more front-end clients destined to a storage system and consolidating the memory access requests to a second number of connections between a network device and the storage system, wherein the second number is less than the first number. In some examples, consolidating the memory access requests includes combining read commands with other read commands destined to the storage system among connections of the first number of connections and combining write commands with other write commands destined to a same storage system among connections of the first number of connections. In some examples, consolidating the memory access requests includes performing protocol conversion to a format accepted by the storage system. In some examples, read or write commands are identified based on content of a header of a received packet, wherein the received packet includes a read or write command.

Network device intermediary for memory access requests

An apparatus is described. The apparatus includes a network interface having a system interface, a media access interface and circuitry to construct a block of null values for a logical block address (LBA) in response to a remote storage system having informed the network interface that the LBA was un-mappable.

Network interface with intelligence to build null blocks for un-mappable logical block addresses

Systems and methods for a controller including controller memory and logic are presented herein. The logic is configured to control access to a persistent storage media and, in response to one or more commands, determine an intermediate parity value based on a first parity calculation by sending a uni-directional command to the persistent storage media. The logic is further configured to store, in the controller memory, the intermediate parity value, and determine a final parity value based on the intermediate parity value and a second parity calculation.

ON-SSD erasure coding with uni-directional commands

Examples described herein relate to a switch comprising a programmable data plane pipeline, wherein the programmable data plane pipeline is configured to provide microservice-to-microservice communications within a service mesh. In some examples, to provide microservice-to-microservice communications within a service mesh, the programmable data plane pipeline is to perform a forwarding operation for a communication from a first microservice to a second microservice. In some examples, to perform a forwarding operation for a communication from a first microservice to a second microservice, the programmable data plane pipeline is to utilize a reliable transport protocol.

Service mesh offload to network devices

Methods and apparatus for end-to-end data plane offloading for distributed storage using protocol hardware and Protocol Independent Switch Architecture (PISA) devices. Hardware-based data plane forwarding is implemented in compute and storage switches that comprise smart server switches running software executing in a kernel and user space. The compute switch is coupled to one or more compute servers/nodes and the storage server is coupled to one or more storage servers or storage arrays. The hardware-based data plane forwarding facilitates an end-to-end data plane between the computer server(s) and storage server(s)/array(s) that is offloaded to hardware. In one example the software comprises Ceph components used to implement control plane operations in connection with hardware offloaded data plane operations, and storage traffic employs the NVMe-oF protocol and the kernels include NVMe-oF modules. In one aspect the hardware-based data plane forwarding is implemented using programmable P4switch chips. In one aspect the storage and server switches are Top of Rack (ToR) switches.

End-to-end data plane offloading for distributed storage using protocol hardware and PISA devices

Examples described herein relate to accessing an initiator as a Non-Volatile Memory Express (NMVe) device. In some examples, the initiator is configured with an address space, configured in kernel or user space, for access by a virtualized execution environment. In some examples, the initiator to copy one or more storage access commands from the virtualized execution environment into a queue for access by a remote direct memory access (RDMA) compatible network interface. In some examples, the network interface to provide Non-Volatile Memory Express over Fabrics (NVMe-oF) compatible commands based on the one or more storage access commands to a target storage device. In some examples, the initiator is created as a mediated device in kernel space or user space of a host system. In some examples, configuration of a physical storage pool address of the target storage device for access by the virtualized execution environment occurs by receipt of the physical storage pool address in a configuration command. In some examples, configuration of the target storage device for access by the virtualized execution environment occurs by receipt of a storage pool internal NVMe Qualified Name in the configuration command.

Intermediary for storage command transfers

Examples described herein relate to offload reliable transport management to a network interface device and store packets to be resent, based on received packet receipt acknowledgements (ACKs), into one or more kernel space queues that are also accessible in user space.

Reliable transport offloaded to network devices

An apparatus is described. The apparatus includes an accelerator to be coupled to a memory region that the accelerator shares with a virtualization environment comprising a guest OS, a guest VM and an SSD device driver. The accelerator is to forward a submission queue doorbell setting made by the SSD device driver in the shared memory to a corresponding submission queue doorbell in an SSD controller.

Shared memory mechanism to support fast transport of SQ/CQ pair communication between SSD device driver in virtualization environment and physical SSD

Systems and methods for a controller including controller memory and logic are presented herein. The logic is configured to control access to a persistent storage media and, in response to one or more commands, the logic determines an intermediate parity value based on a first parity calculation, and using the intermediate parity value determines a final parity value based on the intermediate parity value and a second parity calculation. Determining the intermediate parity value includes sending a uni-directional command to read an old data value from an address indicated in the uni-directional command, perform an exclusive-or operation on the old data value and a new data value indicated in the uni-directional command to determine the intermediate parity value and store, in the persistent storage media, the intermediate parity value at a location associated to an index indicated in the uni-directional command.

On-SSD erasure coding with uni-directional commands

Examples described herein relate to executing a poller to poll for received communications over multiple transport layer protocols from a connection to identify a received communication from one of the multiple transport layer protocols and identify a second received communication from a different one of the multiple transport layer protocols. A change to the different one of the multiple transport layer protocols occurs in response to failure of the one of the multiple transport layer protocols or slow transport rate using the one of the multiple transport layer protocols. In some examples, the poller is executed in user space and transport layer protocol processing of the received communication and second received communication occur in kernel space.

Multi-protocol support for transactions

Examples herein relate to polling for input/output transactions of a network interface or a storage device, or any peripheral device. Some examples monitor clock cycles spent checking for a presence of input/output (I/O) events and processing I/O events and monitor clock cycles spent checking for presence of I/O events without completing an I/O event. Central processing unit (CPU) core utilization can be based on clock cycles spent checking for a presence of I/O events and processing I/O events and clock cycles spent checking for presence of I/O events without completion of an I/O event. For example, if core utilization is below a threshold, frequency of the core can be reduced for performing polling of I/O events. If core utilization is at or above the threshold, frequency of the core can be increased used to performing polling of I/O events.

Adaptive processor resource utilization

Examples described herein relate to a reliable transport protocol for packet transmission using an Address Family of an eXpress Data Path (AF_XDP) queue framework, wherein the AF_XDP queue framework is to provide a queue for received packet receipt acknowledgements (ACKs). In some examples, an AF_XDP socket is to connect a service with a driver for the network device, one or more queues are associated with the AF_XDP socket, and at least one of the one or more queues comprises a waiting queue for received packet receipt ACKs. In some examples, at least one of the one or more queues is to identify one or more packets for which ACKs have been received. In some examples, the network device is to re-transmit a packet identified by a descriptor in the waiting queue based on non-receipt of an ACK associated with the packet from a receiver.

A computer program product, system, and method to manage access to storage resources from multiple applications. A plurality of virtual controllers is generated in a host memory space. Each virtual controller includes at least one virtual namespace that maps to a physical namespace in a physical controller. Applications are assigned to the virtual controllers. For each application of the applications assigned one of the virtual controllers, a virtual submission queue is generated to communicate with the virtual controller assigned to the application. An Input/Output (I/O) request to a target virtual namespace in one of the virtual submission queues is added to a physical submission queue for the physical controller having the physical namespace for which the target virtual namespace was generated.

Growing community of inventors

Shanghai, China

Changpeng Liu