Huawei Technologies Co., Limited

Changming Cui

Yu Zhang

Yu Huang

Bin Deng

Haitao Fu

Junlin Huang

A test circuit transmits input data of a test vector to a data distribution circuit using an input of a test bus, and transmits the input data of the test vector to a scan input channel in a circuit under test using the data distribution circuit. After scan of the circuit under test is completed, output data of the test vector on a scan output channel in the circuit under test is transmitted to an output of the test bus using the data distribution circuit, to complete testing of the circuit under test. A dynamic correspondence between the data distribution circuit and the test bus may be configured based on a specific test solution, so that a test resource can be dynamically allocated.

Test circuit in chip and circuit test method

This disclosure provides methods and apparatuses for testing a tested circuit. In an implementation, a chip test circuit transmits input data of a test vector to a data distribution circuit through an input of a test bus, and transmits the input data of the test vector to a scan input channel of a tested circuit through the data distribution circuit. After scanning of the tested circuit ends, output data of the test vector of the scan output channel of the tested circuit is transmitted to an output of the test bus through the data distribution circuit to complete the test of the tested circuit. A dynamic correspondence between the data distribution circuit and the test bus is implemented by configuring a first selector, so that test resources can be dynamically allocated.

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Shenzhen, China

Changming Cui