Samsung Electronics Co., Ltd.

ChangMin Jeon

Yongkyu Lee

Yongtae Kim

Boyoung Seo

Youngmok Kim

Yongsang Jeong

Kyongsik Yeom

Jongsung Woo

Teakwang Yu

A memory device includes a first bit line configured to supply a first bit line bias voltage, a memory cell transistor having a first operating voltage, a selection transistor having a second operating voltage and configured to control the supply of the first bit line bias voltage to a source of the memory cell transistor, and a second bit line connected to a drain of the memory cell transistor. A level of the first operating voltage is about equal to a level of the second operating voltage.

Memory device

A semiconductor device includes a substrate, a gate structure, source and drain regions, and first and second lightly doped drain (LDD) regions. The source and drain regions are spaced apart and formed in an active region of the substrate at opposite sides of the gate structure. The first LDD region surrounds one side surface and a bottom surface of the drain region and has a first junction depth. The second LDD region surrounds one side surface and a bottom surface of the source region and has a second junction depth less than the first junction depth. The gate structure includes a gate dielectric layer, a gate electrode, and gate spacers respectively disposed on opposite side walls of the gate dielectric layer and the gate electrode. One side wall of the gate dielectric layer and electrode is aligned with one side surface of the first LDD region.

Asymmetric semiconductor device including LDD region and manufacturing method thereof

A semiconductor device includes: a cell area including a cell substrate, a memory cell array, and a first bonding metal pad on the memory cell array, the memory cell array including a plurality of word lines stacked on the cell substrate and a plurality of bit lines on the plurality of word lines; and a peripheral circuit area having the cell area stacked thereon and including a peripheral circuit substrate, a plurality of circuits on the peripheral circuit substrate, and a second bonding metal pad bonded to the first bonding metal pad, wherein the plurality of circuits include: a plurality of planar channel transistors respectively including a channel along a top surface of the peripheral circuit substrate; and at least one recess channel transistor including a channel along a surface of a recess trench arranged in the peripheral circuit.

Semiconductor device and electronic system including the same

A logic embedded nonvolatile memory device is provided which includes a first erase gate line for erasing a plurality of first memory cells; a second erase gate line electrically separated from the first erase gate line and for erasing a plurality of second memory cells; a global erase gate line supplied with an erase voltage; and an erase gate selection switch formed between the first memory cells and the second memory cells, wherein the erase gate selection switch connects the global erase gate line to the first erase gate line or the second erase gate line according to an erase control signal.

Growing community of inventors

Yongin-si, South Korea

ChangMin Jeon