Samsung Electronics Co., Ltd.

Changkyu Seol

Hong Rak Son

Junjin Kong

Pilsang Yoon

Hyejeong So

Sucheol Lee

Jinsoo Lim

Youngdon Choi

Myoungbo Kwak

Byungsuk Woo

Junghwan Choi

Hongrak Son

Seonghyeog Choi

Jiyoup Kim

Jaehun Jang

Younggeon Yoo

Daewook Kim

Donghwan Lee

Dongjin Park

Sungrae Kim

Geunyeong Yu

Kwanghoon Kim

Youngsuk Ra

Myunghoon Choi

Euncheol Kim

Jun Jin Kong

Doohyun Kim

Heewon Lee

Chanik Park

Dong-Min Shin

Hwaseok Oh

Sae-Young Chung

Ilhan Park

Kwanwoo Noh

Youngjun Hwang

Hyeran Kim

Chanho Yoon

Donggi Lee

Seungkyung Ro

Seongnam Kwon

Hyeonwu Kim

Jae Hun Jang

Chisung Oh

Ju-young Jung

Wonyoung Choi

JongHa Kim

Jeongseok Park

Jungsoo Chung

Byung-Suk Woo

Gilyoung Kang

Ju-Young Jung

Junghyun Hong

Cheolmin Park

Byungyong Choi

Sungik Choi

Jaeyong Son

Hyunseuk Yoo

Seonghyeong Choi

Hyeongseok Song

Hyoungbae Ahn

Lanying Zhao

A memory device, an operating method of the memory device, and a test system including the memory device. The memory device may include a decoder group configured to receive a plurality of codewords including a plurality of symbols from outside of the memory device and to decode the plurality of codewords into data patterns, a memory cell array configured to store the data patterns received from the decoder group and including a plurality of memory cells, and an encoder configured to encode the data patterns into the plurality of codewords including the plurality of symbols. The plurality of codewords may include illegal codewords and normal codewords, and the decoder group may be further configured to convert the illegal codewords among the plurality of codewords into fixed patterns, and the encoder may be configured to output the plurality of codewords to the outside of the memory device.

Memory devices, operating methods of the memory devices, and test systems including the memory devices

An electronic device may include a reception circuit configured to generate a plurality of reception data bits based on a voltage level of an analog signal received through a link, and to generate a plurality of bit reliability values indicating probabilities of error occurrence of the plurality of reception data bits based on the voltage level of the analog signal, an alignment circuit configured to group the plurality of reception data bits into a plurality of error correction code (ECC) symbols, and to generate a plurality of symbol reliability values indicating probabilities of error occurrence of the plurality of ECC symbols based on the plurality of bit reliability values, and a decoding circuit configured to correct errors of the plurality of ECC symbols based on the plurality of symbol reliability values.

Electronic devices and methods of operating the same

Disclosed is a method of operating an electronic device which communicates with an external electronic device. The method includes loading first user data including at least one first condition bit, first valid bits, and second valid bits, generating first and second intermediate data based on the first user data with reference to a target conversion rule of a conversion table of the electronic device, which corresponds to the at least one first condition bit, a sum of a first power value corresponding to the first intermediate data and a second power value corresponding to the second intermediate data being less than or equal to a power threshold value, generating first symbol data by performing first encoding on the first intermediate data, generating second symbol data by performing second encoding on the second intermediate data, and providing first encoded data including the first symbol data and the second symbol data.

Transmitting circuit providing encoded data, electronic device including the same, and method of operating the electronic device including the same

A device includes a receiver configured to receive a plurality of Error Correction Code (ECC) codewords transmitted from an external device through a channel including one or more lanes; an ECC decoder configured to generate a plurality of post ECC codewords by performing error correction with respect to the plurality of ECC codewords and generating a first cyclic redundancy check (CRC) codeword based on the plurality of post ECC codewords; a CRC checker configured to determine whether an error exists in the first CRC codeword; and a post ECC decoder configured to, when it is determined that the error exists in the first CRC codeword, generate a second CRC codeword by estimating a remaining error position based on error correction result information received from the ECC decoder and performing remaining error correction with respect to the plurality of post ECC codewords based on the remaining error position.

Error correction device and error correction method

Encoding and decoding apparatuses and methods for implementing multi-mode coding are provided. The apparatus includes a transmitter and a receiver connected to a data bus. When data bursts are converted by the transmitter into codewords each including a plurality of symbols and/or a codeword received by the receiver is recovered as data bursts, maximum transition avoidance (MTA) codeword mappings in which no maximum transition (MT) event occurs between the plurality of symbols and minimum DC current (MDC) codeword mappings related to minimum power consumption of the plurality of symbols are used.

Encoding and decoding apparatuses and methods for implementing multi-mode coding

An electronic device includes a memory storing data from an external source, an application processing unit (APU) transmitting a secret key and public key generation command, an isolated execution environment (IEE) generating a secret key in response to the secret key generation command, generating a public key based on the secret key in response to the public key generation command, and storing the secret key, and a non-volatile memory performing write and read operations depending on a request of the APU. When the data are stored in the memory, the APU transmits a public key request to the IEE and in response the IEE transfers the public key to the APU through a mailbox protocol. The APU generates a ciphertext by performing homomorphic encryption on the data based on an encryption key in the public key, and classifies and stores the public key and the ciphertext in the non-volatile memory.

Electronic device using homomorphic encryption and encrypted data processing method thereof

A receiver that receives a multi-level signal includes a compensation circuit, a sampling circuit, an output circuit and a mode selector. The compensation circuit generates a plurality of data signals and a plurality of reference voltages by compensating intersymbol interference on an input data signal. The sampling circuit generates a plurality of sample signals based on the plurality of data signals and the plurality of reference voltages. The output circuit generates output data based on the plurality of sample signals, and selects a current value of the output data based on a previous value of the output data. The mode selector generates a mode selection signal used to select one of first and second operation modes based on an operating environment. The compensation circuit and the sampling circuit are entirely enabled in the first operation mode, and the compensation circuit and the sampling circuit are partially enabled in the second operation mode.

Receiver receiving multi-level signal, memory device including the same and method of receiving data using the same

Disclosed is an electronic device, which includes an ECC decoder that performs ECC decoding on a flit including a plurality of PAM-4 symbols for each of a plurality of ECC groups, a CRC decoder that performs CRC decoding on the ECC decoded flit to obtain data, and an erasure decoding unit that calculates an LLR for each of the PAM-4 symbols when the CRC decoding fails, extracts an error symbol candidate from among the plurality of PAM-4 symbols for each of the plurality of ECC groups based on the LLR, and performs the ECC decoding again after erasing the error symbol candidate.

Error correction using PAM4 modulation

A transmitter includes an encoder configured to divide a first number of binary input bits of an input data signal into a first bit group and a second bit group, generate a first intermediate bit group and a second intermediate bit group by manipulating the first bit group and the second bit group differently based on a value of the first bit group, and generate a first symbol group and a second symbol group by encoding the first intermediate bit group and the second intermediate bit group, each of the first symbol group and the second symbol group including a plurality of symbols, and each of the plurality of symbols having three different voltage levels. The transmitter includes a driver configured to generate an output data signal by concatenating the first symbol group and the second symbol group.

Transmitter and receiver for 3-level pulse amplitude modulation signaling and system including the same

An electronic circuit converts a receive signal being analog into reception data being digital. The electronic circuit includes a delay circuit that receives a first receive signal and outputs a reference signal, the reference signal being generated by delaying the first receive signal as much as one of a plurality of different timing delays respectively set to a plurality of loops, a sampler that receives a second receive signal and samples the second receive signal based on the reference signal in each of the plurality of loops, a timing skew estimation circuit that outputs a compensation signal for compensating for a timing skew by extracting a statistical characteristic of a plurality of sample data sampled through the sampler and estimating the timing skew based on the statistical characteristic, and a controller that controls an operation of the timing skew estimation circuit.

Circuit configured to compensate for timing skew and operation method thereof

A storage device includes a first memory device including a plurality of first memory cells, a second memory device including a plurality of second memory cells having the same type as the plurality of first memory cells, and a controller that communicates with the first memory device through a first memory interface and communicates with the second memory device through a second memory interface having an operating speed higher than an operating speed of the first memory interface.

Storage device having a controller that communicates with each of two memories through separate interfaces

Provided is a device and method for encoding and decoding to implement maximum transition avoidance coding with minimum overhead. An exemplary device performs encoding and/or decoding, by using sub-block lookup tables representing correlations between some bit values in a data burst and symbols, a combining lookup table selectively interconnecting the sub-block lookup tables based on remaining bit values of the data burst, and a codeword decoding lookup table designating the sub-block lookup tables corresponding to the symbols of each of received codewords.

Devices and methods for encoding and decoding to implement a maximum transition avoidance coding with minimum overhead

A high bandwidth memory system includes a motherboard; and a semiconductor package coupled to the motherboard. The semiconductor package includes a package substrate mounted on the motherboard and including signal lines providing a plurality of channels; a first semiconductor device mounted on the package substrate and including a first physical layer (PHY) circuit; and a second semiconductor device mounted on the package substrate and including a second PHY circuit. The first semiconductor device and the second semiconductor device exchange a data signal with each other through the plurality of channels, the data signal is a multilevel signal having M levels, where M is a natural number greater than 2, and the first PHY circuit compensates for distortion of the channels and performs digital signal processing to compensate for a mismatch between the channels.

High bandwidth memory system using multilevel signaling

Growing community of inventors

Osan-si, South Korea

Changkyu Seol