Samsung Electronics Co., Ltd.

Lg Innotek Co., Ltd.

Sungkyunkwan University

Lg Electronics Inc.

Hyundai Motor Company

Kia Motors Corporation

Harvard College

Snur & Db Foundation

Changhyun Kim

Hyeonjin Shin

Kyung-Eun Byun

Changseok Lee

Keunwook Shin

Yeonchoo Cho

Hyunjae Song

Eunkyu Lee

Seunggeol Nam

Seongjun Park

Yonghoon Kim

Alum Jung

Jaehwan Jung

Ahrum Sohn

Sangwon Kim

Youngwan Seo

Minhyun Lee

Hyunjoo Kim

Hyoa Kang

Jae Mo Sung

Sungjoo An

Sangwoo Kim

Jinseong Heo

Seungwon Lee

Sangsoo Lee

Won Seok Lee

Sang-Woo Kim

Sang-woo Kim

Junho Park

Jeonghyu Yang

Geunwoo Kim

Hosang Park

Janghee Lee

Donhee Ham

Jongyoub Ryu

Dohyun Lee

Baek Hwan Cho

Seon Wook Kim

Johannes Büsing

Eungryeol Seo

Kyungeun Byun

Jeonil Lee

Junghyun Lee

Wonjae Yoon

Changwoo Shin

Kyoung Mu Lee

Jaemo Sung

Houk Jang

Kaoru Yamamoto

Jungeun Lim

Henry Julian Hinton

Van Luan Nguyen

WooJin Shin

Soonwan Chung

Byoungkab Choi

Jongwook Kwon

Junseong Kim

Myungheon Kang

Derek Daehyun Ji

Soohoon Lee

Sojeong Kim

Jisook Lee

Yoonah Paik

Bee Lim

Sunguk Lim

A modular refrigerator including a main cabinet, and a sub-cabinet selectively coupleable to a right side, an upper side, and a left side, of the main cabinet. The main cabinet includes a cooling unit, a first connection duct for cold air generated by the cooling unit to flow toward the right side, a second connection duct for the cold air to flow toward the upper side, and a third connection duct for the cold air to flow toward the left side. The sub-cabinet includes a first branch duct that, when the sub-cabinet is coupled to the right side, communicates with the first connection duct, a second branch duct that, when the sub-cabinet is coupled to the upper side, communicates with the second connection duct, and a third branch duct that, when the sub-cabinet is coupled to the left side, communicates with third connection duct.

Module refrigerator

A vertical channel transistor includes a first source/drain electrode; a second source/drain electrode spaced apart from the first source/drain electrode in a first direction; a first channel pattern between the first source/drain electrode and the second source/drain electrode; a first gate electrode on a side surface of the first channel pattern; a first gate insulation layer between the first channel pattern and the first gate electrode; and a first graphene insertion layer between the first source/drain electrode and the first channel pattern.

Vertical channel transistor including a graphene insertion layer beweeen a source/drain electrode and a channel pattern

Provided is a thin film structure including a substrate, a metal layer on the substrate and spaced apart from the substrate, and a two-dimensional material layer between the substrate and the metal layer. The two-dimensional material layer may be configured to limit and/or block an electron transfer between the substrate and the metal layer. A resistivity of a metal layer on the two-dimensional material layer may be lowered by the two-dimensional material layer.

Thin film structure and electronic device including two-dimensional material

Provided are a signal processing device and an image display apparatus including the same. The signal processing device and the image display apparatus including the same include: a signal processormay include an OSC processor configured to upscale an OSC having a first resolution to a second resolution greater than the first resolution; and a synthesizer configured to synthesize at least a part of an image having the second resolution and the upscaled OSD having the second resolution, and the OSD processor outputs the OSD having the second resolution, in which luminance and transparency are adjusted.

Signal processing device and image display apparatus including the same capable of increasing clarity of OSD when mixing with image

Provided are a vertical-channel cell array transistor structure and a dynamic random-access memory (DRAM) device including the same. The vertical-channel cell array transistor structure includes a semiconductor substrate, a plurality of channels arranged in an array on the semiconductor substrate and each extending perpendicularly from the semiconductor substrate, a gate insulating layer on the plurality of channels, a plurality of word lines on the semiconductor substrate and extending in a first direction, and a two-dimensional (2D) material layer on at least one surface of each of the plurality of word lines.

Vertical-channel cell array transistor structure and dram device including the same

A semiconductor device includes a first source/drain structure including a first semiconductor region and a first electrode in electrical contact with the first semiconductor region; a second source/drain structure including a second semiconductor region and a second electrode in electrical contact with the second semiconductor region; a channel between the first semiconductor region and the second semiconductor region; and a gate structure including a gate insulating film covering the channel and a gate electrode covering the gate insulating film. The first source/drain structure further includes a silicide film between the first semiconductor region and the first electrode and a conductive barrier between the silicide film and the first electrode. The conductive barrier includes a conductive two-dimensional material.

Semiconductor device and electronic apparatus including the semiconductor device

A dishwasher including a tub provided in the cabinet to form a washing chamber, and a drying apparatus arranged on a side wall of the tub and including a flow path provided to allow air sucked from the washing chamber to flow, a heater arranged in the flow path to heat air in the flow path, and a switch arranged upstream of the heater to turn off the heater in response to air, which is adjacent to the heater, reaching a predetermined temperature.

Dishwasher including a drying apparatus

Disclosed is a neural computer including an image sensor capable of controlling a photocurrent. The neural computer according to an embodiment includes a preprocessor configured to receive an image and generate a feature map for the received image; a flattening unit configured to transform the feature map generated by the preprocessor into tabular data to provide data output; and an image classifier configured to classify images received through the preprocessor by using the data output by the flattening unit as an input value. The preprocessor includes an optical signal processor configured to receive the image and generate the feature map.

Neural computer including image sensor capable of controlling photocurrent

A method of forming graphene includes: preparing a substrate in a reaction chamber; performing a first growth process of growing a plurality of graphene aggregates apart from each other on the substrate at a first growth rate by using a reaction gas including a carbon source; and performing a second growth process of forming a graphene layer by growing the plurality of graphene aggregates at a second growth rate slower than the first growth rate by using the reaction gas including the carbon source.

Method of forming graphene

Disclosed is a memory device including a plurality of memory banks, each of which performs an operation based on first operand data including pieces of first unit data and second operand data including pieces of second unit data and a processing in-memory interface unit (PIM IU) that delivers signals for an operation request to the plurality of memory banks. Each of the plurality of memory banks includes a memory cell array configured to store one of the pieces of first unit data and a PIM engine that reads the one of the pieces of first unit data from the memory cell array, reads the pieces of second unit data broadcast to the plurality of memory banks, and generates an operation result by performing an operation based on the one of the pieces of first unit data and the pieces of second unit data.

Memory device performing in-memory operation and method thereof

An electronic device, according to various embodiments of the present disclosure, may comprise: a housing including a seating groove therein; a battery seated in the seating groove, at least a partial area of which includes a curved surface; and an adhesive member disposed between the battery and the seating groove and formed along at least a portion of an edge of the battery. The adhesive member may be formed having varied predetermined thicknesses, corresponding to a position of the battery.

Battery adhesive structure and electronic device comprising same

Disclosed herein are a method of forming a transition metal dichalcogenide thin film and a method of manufacturing a device including the same. The method of forming a transition metal dichalcogenide thin film includes: depositing a transition metal dichalcogenide thin film on a substrate; and heat-treating the deposited transition metal dichalcogenide thin film.

Method of forming transition metal dichalcogenidethin film and method of manufacturing electronic device including the same

Disclosed herein are a method of forming a transition metal dichalcogenide thin film and a method of manufacturing a device including the same. The method of forming a transition metal dichalcogenide thin film includes: providing a substrate in a reaction chamber; depositing a transition metal dichalcogenide thin film on the substrate using a sputtering process that uses a transition metal precursor and a chalcogen precursor and is performed at a first temperature; and injecting the chalcogen precursor in a gas state and heat-treating the transition metal dichalcogenide thin film at a second temperature that is higher than the first temperature. The substrate may include a sapphire substrate, a silicon oxide (SiO) substrate, a nanocrystalline graphene substrate, or a molybdenum disulfide (MoS) substrate.

Method of forming transition metal dichalcogenide thin film

A method of selectively growing graphene includes forming an ion implantation region and an ion non-implantation region by implanting ions locally into a substrate; and selectively growing graphene in the ion implantation region or the ion non-implantation region.

Method of growing graphene selectively

Provided are an interconnect structure and an electronic device including the interconnect structure. The interconnect structure includes a dielectric layer including at least one trench, a conductive wiring filling an inside of the at least one trench, and a cap layer on at least one surface of the conductive wiring. The cap layer includes nanocrystalline graphene. The nanocrystalline includes nano-sized crystals.

Interconnect structure having nanocrystalline graphene cap layer and electronic device including the interconnect structure

Growing community of inventors

Seoul, South Korea

Changhyun Kim