Samsung Electronics Co., Ltd.

Changhyun Cho

Keunnam Kim

Yoosang Hwang

Yong Kwan Kim

Myeong-Dong Lee

Jimin Choi

Si-Ho Song

Dongryul Lee

Minseong Choi

Sunyoung Park

Jeonghee Park

Hyeongsun Hong

Hyeon-Woo Jang

Jin-Won Jeong

Kyehee Yeom

Youngbae Kim

Dueung Kim

A three-dimensional semiconductor memory device includes first conductive lines extending horizontally in a first direction, a second conductive line extending vertically in a second direction perpendicular to the first direction, and memory cells at cross-points between the first conductive lines and the second conductive line. The first conductive lines are laterally spaced apart from each other in a third direction crossing the first direction. Each of the memory cells includes a variable resistance element and a switching element that are horizontally arranged. The variable resistance element includes a first variable resistance pattern and a second variable resistance pattern arranged in the second direction, a first electrode between the first variable resistance pattern and the first conductive line, a second electrode between the second variable resistance pattern and the second conductive line, and a third electrode between the first variable resistance pattern and the second variable resistance pattern.

Three dimensional semiconductor memory devices

According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.

Semiconductor devices and methods of fabricating the same

A nonvolatile memory device includes a memory cell array, a word line drive block that is connected to a first group of memory cells through a first group of word lines and to a second group of memory cells through a second group of word lines, a bit line bias and sense block that is connected to the first and second groups of memory cells through bit lines, a variable current supply block that generates a word line current to be supplied to a selected word line, and a control logic block that receives an address and a command and controls the variable current supply block to adjust an amount of the word line current based on the address. The control logic block further varies the amount of the word line current depending on a distance between the selected word line and the substrate.

Nonvolatile memory device

Provided are semiconductor devices and methods of fabricating the same. In methods of forming the same, an etch stop pattern and a separate spacer can be formed on a sidewall of a bit line contact, wherein the etch stop pattern and the separate spacer each comprise material having an etch selectivity relative to an oxide. A storage node contact plug hole can be formed so that the etch stop pattern and the separate spacer form a portion of a sidewall of the storage node contact plug hole spaced apart from the bit line contact. The storage node contact plug hole can be cleaned to remove a natural oxide formed in the storage node contact plug hole. Related devices are also disclosed.

Methods of fabricating semiconductor devices

Semiconductor devices

Growing community of inventors

Yongin-si, South Korea

Changhyun Cho