International Business Machines Corporation

Globalfoundries Inc.

Lg Electronics Inc.

Changhwan Choi

Vijay Narayanan

Takashi Ando

Martin Michael Frank

Unoh Kwon

Kisik Choi

Vamsi Krishna Paruchuri

Hemanth Jagannathan

Sufi Zafar

Paul Charles Jamison

Lisa F Edge

Bruce Bennett Doris

Josephine B Chang

Michael A Guillorn

Praneet Adusumilli

Eduard Albert Cartier

James N Pan

Alessandro Cesare Callegari

Young-Hee Kim

Ilhyun Kim

Elizabeth A Duch

A mobile terminal comprises: a body frame that is expandable in a first direction and shrinkable in a second direction; a flexible display in which the area of a display unit positioned on the front surface of the body frame is expanded according to the expansion of the body frame; a driving unit that changes the size of the body; a sensing unit that senses a user command; and a control unit that controls the driving unit to expand or shrink the body frame on the basis of the user command sensed by the sensing unit. Thus, a screen of the display unit positioned on the front surface can be expanded through size adjustment. Because a part of the screen always faces the outside, a separate secondary display unit is not required, and the screen may be expanded step by step as needed.

Mobile terminal

A replacement metal gate process in which a high-k dielectric is applied. The high-k dielectric may be doped with lanthanum in an NMOS region or aluminum in a PMOS region. A dummy gate structure may be formed over the high-k dielectric and etched to form an opening over the NMOS region and an opening over the PMOS region. Thereafter, first work function metals are deposited in the NMOS opening and second work function metals are applied in the PMOS openings. A suitable gate electrode material may then fill the remainder of the NMOS and PMOS openings.

Low threshold voltage CMOS device

A replacement metal gate process in which a high-k dielectric is applied. The high-k dielectric may be doped with lanthanum in an NMOS region or aluminum in a PMOS region. Alternatively, after a dummy gate is removed in the NMOS and PMOS regions to leave openings in the NMOS and PMOS regions, lanthanum oxide may be deposited in the NMOS opening or aluminum oxide deposited in the PMOS opening. Thereafter, first work function metals are deposited in the NMOS opening and second work function metals are applied in the PMOS openings. A suitable gate electrode material may then fill the remainder of the NMOS and PMOS openings.

A method of forming a semiconductor structure. The semiconductor structure has a semiconductor substrate and an nFET and a pFET disposed upon the substrate. The pFET has a semiconductor SiGe channel region formed upon or within a surface of the semiconductor substrate and a gate dielectric having an oxide layer overlying the channel region and a high-k dielectric layer overlying the oxide layer. A gate electrode overlies the gate dielectric and has a lower metal layer abutting the high-k layer, a scavenging metal layer abutting the lower metal layer, and an upper metal layer abutting the scavenging metal layer. The metal layer scavenges oxygen from the substrate (nFET) and SiGe (pFET) interface with the oxide layer resulting in an effective reduction in Tand Vof the pFET, while scaling Tinv and maintaining Vt for the nFET, resulting in the Vof the pFET becoming closer to the Vof a similarly constructed nFET with scaled Tvalues.

Fabrication of low threshold voltage and inversion oxide thickness scaling for a high-k metal gate p-type MOSFET

Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.

Structure and method to obtain EOT scaled dielectric stacks

A semiconductor device including an NMOS region and a PMOS region; the NMOS region having a gate structure including a first high-k gate dielectric, a first work function setting metal and a gate electrode fill material; the PMOS region having a gate structure comprising a second high-k gate dielectric, a second work function setting metal and a gate electrode fill material; wherein the first gate dielectric is different than the second gate dielectric and the first work function setting metal is different than the second work function setting metal. Also disclosed are methods for fabricating the semiconductor device which include a gate last process.

A field effect transistor device includes a first gate stack portion including a dielectric layer disposed on a substrate, a first TiN layer disposed on the dielectric layer, a metallic layer disposed on the dielectric layer, and a second TiN layer disposed on the metallic layer, a first source region disposed adjacent to the first gate stack portion, and a first drain region disposed adjacent to the first gate stack portion.

Scaled equivalent oxide thickness for field effect transistor devices

A field effect transistor device and method which includes a semiconductor substrate, a dielectric gate layer, preferably a high dielectric constant gate layer, overlaying the semiconductor substrate and an electrically conductive oxygen barrier layer overlaying the gate dielectric layer. In one embodiment, there is a conductive layer between the gate dielectric layer and the oxygen barrier layer. In another embodiment, there is a low resistivity metal layer on the oxygen barrier layer.

Field-effect transistor device having a metal gate stack with an oxygen barrier layer

A stack of a high-k gate dielectric and a metal gate structure includes a lower metal layer, a scavenging metal layer, and an upper metal layer. The scavenging metal layer meets the following two criteria 1) a metal (M) for which the Gibbs free energy change of the reaction Si+2/y MO&#x2192;2x/y M+SiOis positive 2) a metal that has a more negative Gibbs free energy per oxygen atom for formation of oxide than the material of the lower metal layer and the material of the upper metal layer. The scavenging metal layer meeting these criteria captures oxygen atoms as the oxygen atoms diffuse through the gate electrode toward the high-k gate dielectric. In addition, the scavenging metal layer remotely reduces the thickness of a silicon oxide interfacial layer underneath the high-k dielectric. As a result, the equivalent oxide thickness (EOT) of the total gate dielectric is reduced and the field effect transistor maintains a constant threshold voltage even after high temperature processes during CMOS integration.

Scavanging metal stack for a high-k gate dielectric

A method for forming a field effect transistor device includes forming an oxide layer on a substrate, forming a dielectric layer on the oxide layer, forming a first TiN layer on the dielectric layer, forming a metallic layer on the first layer, forming a second TiN layer on the metallic layer, removing a portion of the first TiN layer, the metallic layer, and the second TiN layer to expose a portion of the dielectric layer, forming a layer of stoichiometric TiN on the exposed portion of the dielectric layer and the second TiN layer, heating the device, and forming a polysilicon layer on the device.

In one embodiment, the invention is a method and apparatus for fabricating a high-performance band-edge complementary metal-oxide-semiconductor device. One embodiment of a method for fabricating a complementary metal-oxide-semiconductor device includes fabricating an n-type metal-oxide-semiconductor device using a gate first process, and fabricating a p-type metal-oxide-semiconductor device using a gate last process.

Growing community of inventors

Seoul, South Korea

Changhwan Choi