Qualcomm Incorporated

Changho Jung

Chulmin Jung

Arun Babu Pallerla

Nishith Nitin Desai

Sei Seung Yoon

Rakesh Vattikonda

Esin Terzioglu

Sonia Ghosh

Tony Chung Yiu Kwok

Keejong Kim

Nan Chen

Zhiqin Chen

Ritu Chaba

Anil Chowdary Kota

Sung Son

Derek Yang

Percy Dadabhoy

Shahzad Nazar

Haining S Yang

Zhongze Wang

Venugopal Boynapalli

Cheng Zhong

Frank Guo

Fahad Ahmed

Dongkyu Park

Po-Hung Chen

Yandong Gao

David Li

Balachander Ganesan

Alex Dongkyu Park

Peng Jin

Jason Cheng

Nishith Desai

A pseudo-triple-port memory is provided with read datapaths and write datapaths. The pseudo-triple-port memory includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port coupled to a first bit line, a second read port coupled to a second bit line, and a write port coupled to the first bit line and to the second bit line.

Method of pseudo-triple-port SRAM datapaths

A memory is provided with a clock circuit configured to simultaneously assert a write multiplexer clock signal and a read multiplexer clock signal during a scan mode of operation. In the scan mode of operation, a scan in signal routes through a write multiplexer to a first bit line while the write multiplexer clock signal is asserted. Similarly, the scan in signal routes from the first bit line through a read multiplexer while the read multiplexer clock signal is asserted.

SRAM with scan mode

Various implementations provide systems and methods for reading data from memory bit cells. An example implementation includes a read circuit that provides a single-ended output from a sensing stage. The single-ended output is received by a reset-set (RS) latch, which also receives a virtual bit line signal. The single-ended output and the virtual bit line signal provide complementary inputs to the RS latch, and the RS latch stores a sensed bit, and the sensed bit may be driven onto a data bus.

Memory with single-ended sensing using reset-set latch

A memory is provided that is configured to practice two different modes of read operation, such as both a normal read operation and a burst-mode read operation. In one example, the memory is a pseudo-dual-port memory. The memory may include an address comparator to perform a time-division multiplexing to first compare a read address to a stored address and then to compare a write address to the stored address.

Pseudo-dual-port SRAM with burst-mode address comparator

Pseudo-triple-port SRAM datapaths

A memory is provided that is configured to practice both a conventional normal read operation and also a burst mode read operation. During the normal read operation, the memory pre-charges the bit lines in a group of multiplexed columns. Each column has a sense amplifier that latches a bit decision for the column during the normal read operation. If a subsequent read operation addresses the same group of multiplexed columns, the memory invokes the burst-mode read operation during which the bit lines are not pre-charged.

SRAM with burst mode operation

A memory is provided that is configured to practice both a normal read operation and also a burst mode read operation. A column multiplexer selects from a plurality of columns using a pair of pass transistor for each column. The column multiplexer drives a true input node and a complement input node of an output data latch.

Burst-mode memory with column multiplexer

A charge-transfer transistor couples between a bit line and a sense node for a sense amplifier. During a read operation, a charge-transfer driver drives a gate voltage of the charge-transfer transistor to control whether the charge-transfer transistor conducts during a charge-transfer period. To assist the charge-transfer by the charge-transfer transistor, a first and second cross-coupled transistor are coupled between the bit line and a complement bit line.

SRAM with robust charge-transfer sense amplification

A pseudo-triple-port memory is provided that includes a plurality of pseudo-triple-port bitcells, each pseudo-triple-port first bitcell having a first read port including a first word line coupled to a first bit line through a first access transistor, a second read port including a second word line coupled to a second bit line through a second access transistor, and a write port including both the word lines, both the bit lines, and the pair of access transistors.

Pseudo-triple-port SRAM

A bitcell architecture for a pseudo-triple-port memory is provided that includes a a bitcell arranged on a semiconductor substrate, the bitcell defining a bitcell width and a bitcell height and including a first access transistor and a second access transistor. A first metal layer adjacent the semiconductor substrate is patterned to form a pair of local bit lines arranged within the bitcell width. The pair of local bit lines includes a local bit line coupled to a terminal of the first access transistor and includes a complement local bit line coupled to a terminal of the second access transistor.

Pseudo-triple-port SRAM bitcell architecture

A word line decoder for pseudo-triple-port memory is provided that includes a first logic gate for decoding a word line address to a first word line in a word line pair and a first word line clock signal. The decoder further includes a second logic gate for decoding a word line address to a second word line in the word line pair and a second word line clock signal.

Decoding for pseudo-triple-port SRAM

A memory is provided that is configured to practice both a normal read operation and also a burst mode read operation. A burst mode address comparator compares a current row address to a preceding row address from a preceding read operation to determine whether a read operation is a normal read operation or a burst mode read operation. The burst mode address comparator invokes the burst mode despite the presence of an intervening write operation to a row address not equal to the preceding row address.

SRAM with advanced burst mode address comparator

Certain aspects of the present disclosure are directed to a memory system. The memory system generally includes a word line (WL) driver circuit comprising a transistor coupled between a WL of a memory and a reference potential node. The memory system also includes a clamping circuit having logic configured to generate a control signal to drive a gate of the transistor such that the control signal is floating when the first head switch is open, and a first head switch coupled between a voltage rail and a supply input of the logic.

Techniques for reducing rock bottom leakage in memory

According to certain aspects, a method includes receiving an input test signal at a test input, receiving an event signal, and passing the input test signal to a test output or blocking the input test signal from the test output based on the event signal. In certain aspects, the event signal indicates an occurrence of an event in a circuit block (e.g., a memory, a processor, or another type of circuit block). The event may include a precharge operation, opening of input latches, reset of a self-time loop, arrival of a data value at a flop in a signal path, an interrupt signal indicating an error or failure in the circuit block, or another type of event.

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San Diego, CA, United States of America

Changho Jung