Skhynix Inc.

Industry-University Cooperation Foundation Hanyang University

Ginno Games Inc.

Changhan Kim

In Ku Kang

Sun Young Kim

Kun Young Lee

Sung Hyun Yoon

Daehyun Kim

Jinseon Lee

Woo-Hee Kim

Jooyoung Lee

Sangkyun Kim

Yun Cheol Han

Kyumin Lee

Sungkwan Hong

Dae Hyun Kim

Jeong-Min Lee

Soon Ju Lee

Ga Ram Choi

There are provided a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a doped semiconductor layer including an upper surface facing a first direction, a multifunctional stack including a plurality of interlayer insulating layers and a plurality of conductive layers stacked alternately with each other in the first direction above the doped semiconductor layer, the multifunctional stack including a groove, a liner insulating layer on a bottom surface of the groove, a liner semiconductor layer on the liner insulating layer, and a first electrode and a second electrode spaced apart from each other in the groove and extending in the first direction from the liner semiconductor layer.

Semiconductor memory device and manufacturing method of semiconductor memory device

A semiconductor device may include: a gate structure including insulating layers and control gates, which are alternately stacked; a channel layer penetrating the gate structure; floating gates respectively located between the control gates and the channel layer; first blocking patterns respectively located between the control gates and the floating gates; and a second blocking pattern located between the first blocking patterns and the control gates and between the control gates and the insulating layers, the second blocking pattern including a material with a dielectric constant that is higher than that of the first blocking patterns.

Semiconductor device and manufacturing method of semiconductor device

An area-selective deposition method may include providing a substrate structure including a silicon oxide area and a silicon nitride area; performing a surface treatment on the silicon oxide area and the silicon nitride area of the substrate structure to form a first functional group on a surface of the silicon oxide area and to form a second functional group on a surface of the silicon nitride area; and performing an atomic layer deposition (ALD) process in a chamber in which the substrate structure is disposed, to selectively form a silicon oxide layer on the silicon oxide area among the silicon nitride area and the silicon oxide area. The ALD process may include: supplying an aminosilane-based silicon precursor into the chamber; purging the chamber with a first purge gas; supplying an oxygen-containing source into the chamber; and purging the chamber with a second purge gas.

Method of area-selective deposition and method of fabricating an electronic device using the same

A semiconductor device includes a stacked structure with insulating layers and conductive layers that are alternately stacked on each other, a hard mask pattern on the stacked structure, a channel structure penetrating the hard mask pattern and the stacked structure, insulating patterns interposed between the insulating layers and the channel structure, wherein the insulating patterns protrude farther towards the channel structure than a sidewall of the hard mask pattern, and a memory layer interposed between the stacked structure and the channel structure, wherein the memory layer fills a space between the insulating patterns.

Method of forming a stacked memory structure with insulating patterns

A semiconductor device includes a stacked structure including conductive layers and gaps respectively interposed between the conductive layers, a channel layer passing through the stacked structure, a ferroelectric layer surrounding a sidewall of the channel layer, and first dielectric patterns interposed between the ferroelectric layer and the conductive layers, respectively. The gaps extending between the first dielectric patterns.

Semiconductor device and manufacturing method of the semiconductor device

A deposition method may include: providing a structure to be deposited that includes a silicon oxide area and a silicon nitride area having different surface characteristics from each other; and performing an atomic layer deposition (ALD) process in a reactor provided with the structure to selectively form a silicon oxide layer on the silicon oxide portion between the silicon oxide portion and the silicon nitride portion. The ALD process may include: supplying a silicon precursor into the reactor to selectively adsorb the silicon precursor to a surface of the silicon oxide portion; purging the reactor; supplying an inhibitor material into the reactor to selectively adsorb the inhibitor material to a surface of the silicon nitride portion; purging the reactor; supplying an oxygen-containing source into the reactor; and purging the reactor.

Method of deposition and method of fabricating electronic device using the same

A semiconductor device includes a stacked structure including conductive layers and insulating layers stacked alternately with each other, a channel layer passing through the stacked structure, a ferroelectric layer surrounding a sidewall of the channel layer, a first dielectric layer surrounding a sidewall of the ferroelectric layer, and sacrificial patterns interposed between the first dielectric layer and the insulating layers and including a material with a higher dielectric constant than the first dielectric layer.

A semiconductor device includes: a gate structure including conductive layers and insulating layers, which are alternately stacked; a channel layer penetrating the gate structure; memory patterns respectively located between the channel layer and the conductive layers; a blocking layer including first parts located between the conductive layers and the memory patterns and second parts extending between the memory patterns; and air gaps respectively located between the blocking layer and the insulating layers.

A semiconductor device includes: a gate structure including conductive layers and insulating layers, which are alternately stacked; a channel layer penetrating the gate structure; memory patterns respectively located between the channel layer and the conductive layers; a blocking layer including first parts located between the memory patterns and the conductive layers, and second parts extending between the memory patterns and protruding toward the insulating layers to the inside of the gate structure; and air gaps including a first region located in the second parts and a second region located between the memory patterns.

A semiconductor device includes: a gate structure including conductive layers and insulating layers, which are alternately stacked; a channel layer penetrating the gate structure; memory patterns respectively located between the channel layer and the conductive layers; air gaps located between the memory patterns; and a sealing layer including first parts respectively including the air gaps and a second part extending between the memory patterns.

A semiconductor device includes a stacked structure with insulating layers and conductive layers that are alternately stacked on each other, a hard mask pattern located on the stacked structure, a channel structure penetrating the hard mask pattern and the stacked structure, insulating patterns interposed between the insulating layers and the channel structure, and a memory layer interposed between the stacked structure and the channel structure, wherein the memory layer fills a space between the insulating patterns, wherein a sidewall of each of the conductive layers protrudes farther towards the channel structure than a sidewall of the hard mask pattern, and wherein the insulating patterns protrude farther towards the channel structure than the sidewall of each of the conductive layers.

Stacked memory structure with insulating patterns

A semiconductor device includes a stacked structure including insulating layers and conductive layers alternately stacked on each other, a hard mask pattern located on the stacked structure, a channel structure passing through the hard mask pattern and the stacked structure, insulating patterns interposed between the insulating layers and the channel structure and each including a first surface and a second surface, wherein the first surface faces each of the insulating layers and is flat and the second surface faces the channel structure and includes a curved surface, and a memory layer interposed between the stacked structure and the channel structure and filling a space between the insulating patterns, wherein a sidewall of each of the conductive layers is located on an extending line of a sidewall of the hard mask pattern and the insulating patterns protrude farther towards the channel structure than the sidewall of the hard mask pattern.

Growing community of inventors

Icheon-si, South Korea

Changhan Kim