Samsung Electronics Co., Ltd.

Changbum Kim

Sunghoon Kim

Daeseok Byeon

Seungyeon Kim

A semiconductor device includes a plurality of semiconductor elements, each of the plurality of semiconductor elements including an active region disposed on a substrate, and a gate structure intersecting the active region and extending in a first direction that is parallel to an upper surface of the substrate; and at least one dummy element disposed between a pair of semiconductor elements adjacent to each other in a second direction, intersecting the first direction, among the plurality of semiconductor elements. The dummy element includes a dummy active region and at least one dummy gate structure intersecting the dummy active region and extending in the first direction. A length of the dummy active region in the second direction is less than a length of the active region included in each of the pair of semiconductor elements.

Semiconductor device and memory device including a dummy element

A non-volatile memory device includes a first semiconductor layer and a second semiconductor layer arranged in the vertical direction. A first semiconductor layer includes a plurality of memory cells, and a plurality of metal lines extending in a first direction, and including first bit lines, second bit lines, and a common source line tapping wire between the first bit lines and the second bit lines. A second semiconductor layer includes a page buffer circuit connected to the first bit lines and the second bit lines, and the page buffer circuit includes first transistors arranged below the first bit lines and electrically connected to the first bit lines, second transistors arranged below the second bit lines and electrically connected to the second bit lines, and a first guard ring arranged below and overlapped the common source line tapping wire in the vertical direction and extending in the first direction.

Non-volatile memory device

A semiconductor device includes a cell region and a peripheral circuit region. The cell region includes gate electrode layers stacked on a substrate, channel structures extending in a first direction, extending through the gate electrode layers, and connected to the substrate, and bit lines extending in a second direction and connected to the channel structures above the gate electrode layers. The peripheral circuit region includes page buffers connected to the bit lines. Each page buffer includes a first and second elements adjacent to each other in the second direction and sharing a common active region between a first gate structure of the first element and a second gate structure of the second element in the second direction. Boundaries of the common active region include an oblique boundary extending in an oblique direction forming an angle between 0 and 90 degrees with the second direction.

Semiconductor device

A semiconductor device includes a gate line extending in a first direction, parallel to an upper surface of a semiconductor substrate; a first active region including a first channel region disposed below the gate line and including a first conductivity-type impurity; a second active region disposed to be separated from the first active region in the first direction, including a second channel region disposed below the gate line, and including the first conductivity-type impurity; and a plurality of metal wirings disposed at a first height level above the semiconductor substrate, wherein at least one metal wiring, among the plurality of metal wirings, is directly electrically connected to the first active region, no metal wirings at the first height level are electrically connected to the second active region, and at least one metal wiring, among the plurality of metal wirings, is connected to receive a signal applied to the gate line.

A memory device including a first memory cell array including first memory cells stacked vertically on a first memory cell array region of a top surface of a substrate; a second memory cell array including second memory cells stacked vertically on a second memory cell array region of the top surface; first word lines coupled to the first memory cells and including a subset of first word lines and remaining first word lines; second word lines coupled to the second memory cells and including a subset of second word lines and remaining second word lines; and a row decoder, including a plurality of merge pass transistors each commonly connected to a respective one of the subset of first word lines and a respective one of the subset of second word lines, disposed in a region of the top surface between the first and second cell array regions.

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Seoul, South Korea

Changbum Kim