Cirrus Logic Inc.

Intel Corporation

Sematech, Inc.

Chang Yong Kang

John L Melanson

Pierre Laurent

Hari K Tadepalli

Prasad M Ghatigar

Serge Zhilyaev

Ioannis T Schoinas

Johann Guy Gaboriau

Michael T Klinglesmith

Lingli Zhang

Darren L Abramson

David Gilmer

Robert De Gruijl

Paul Daniel Kirsch

Khee Wooi Lee

Sangduk Park

T J O'Dwyer

Joel Barnett

Jun Hao

Chanro Park

Tj O'Dwyer

Robert DeGruijl

Methods and apparatuses relating to tightly-coupled heterogeneous computing are described. In one embodiment, a hardware processor includes a plurality of execution units in parallel, a switch to connect inputs of the plurality of execution units to outputs of a first buffer and a plurality of memory banks and connect inputs of the plurality of memory banks and a plurality of second buffers in parallel to outputs of the first buffer, the plurality of memory banks, and the plurality of execution units, and an offload engine with inputs connected to outputs of the plurality of second buffers.

Hardware processors and methods for tightly-coupled heterogeneous computing

A processing system implementing techniques for parallelized authentication encoding is provided. In one embodiment, the processing system includes an accumulator, a register representing a pipeline stage and a processing core coupled to the accumulator and to the register. The processing core is to split an input message into a first input stream and a second input stream. For each input stream, the processing core is further to add, to the accumulator, a data block from the input stream. Contents of the accumulator multiplied by a squared nonce value are stored in the register and a result of applying a modulo reduction operation to the contents of the register is stored in the accumulator. Thereupon, an authentication tag for the input message is generated based on the result stored in the accumulator and the contents of the register.

Parallelized authentication encoding

In one embodiment, a system includes: a first root space associated with a first root space identifier and including at least one first host processor and a first agent, the at least one first host processor and the first agent associated with the first root space identifier; a second root space associated with a second root space identifier and including at least one second host processor and a second agent, the at least one second host processor and the second agent associated with the second root space identifier; and a shared fabric to couple the first root space and the second root space, the shared fabric to route a transaction to the first root space or the second root space based at least in part on a root space field of the transaction. Other embodiments are described and claimed.

Providing multiple roots in a semiconductor device

Capacitors, systems, and methods are disclosed. In one embodiment, the capacitor includes a first electrode. The capacitor may also include a first insulator layer having a positive VCC adjacent to the first electrode. The capacitor may further include a second insulator layer having a negative VCC adjacent to the first insulator layer. The capacitor may also include a third insulator layer having a positive VCC adjacent to the second insulator layer. The capacitor may also include a second electrode adjacent to the third insulator layer.

Capacitors, systems, and methods

A method of controlling noise in a pulse width modulation circuit includes varying a sample frequency and a range of information levels, wherein each sample within a data sample stream at the sample frequency represents a level within the range of information levels, to shift in frequency noise generated at the sample frequency during encoding of the data sample stream into pulse width modulated patterns.

Circuits and methods for controlling switching noise in switched-mode circuits

A data processing system including an input data port for receiving input data samples asynchronous to a native clock signal and having an input sample rate, a first sample rate converter for converting the data samples from the input sample rate to a sample rate synchronous with a rate of the native clock signal, and a data converter for converting data samples output from the first sample rate converter to another format. An analog to digital converter converts an analog signal into output data samples with a sample rate synchronous with the rate of the native clock signal, and a second sample rate converter converts the sample rate of the output data samples from the sample rate synchronous with the rate of the native clock signal to an output sample rate such that output data samples are asynchronous to the native clock signal.

Circuits and methods for noise management in systems including an asynchronously-operable data port

Digital to Analog Conversion and sample conversion blocks are combined in order to reduce hardware and/or computational complexity. A novel DSM design is used to perform sample rate conversion. The DSM may also be used to perform other digital filtering functions, thus providing a single hardware/software technique to perform both functions. The invention includes a method and apparatus for converting input data samples provided at a first sample rate to an analog output signal. Input data samples are converted by a Delta Sigma Modulator (DSM) in a Digital to Analog Converter (DAC) to output data samples, where internal states of the DSM are updated at a second sample rate unequal to the first sample rate. At least one internal state of the DSM s modified to account for the time difference in response to a new input sample arriving at a time different from an update of the internal states of the DSM.

Sample rate conversion combined with DSM

An apparatus and method for memory transaction buffering are implemented. Read and write buffer units are provided. The read buffer unit is configured for storing at least one data value read from a memory device, and the write buffer unit is configured for storing at least one data value for writing to the memory device. The read buffer unit is operable for updating with the at least one data value for writing to the memory device in response to a write to the write buffer unit.

Systems and methods for buffering memory transactions

Growing community of inventors

Chandler, AZ, United States of America

Chang Yong Kang