Fairchild Korea Semiconductor Ltd.

Samsung Sdi Co., Inc.

Chang-wook Kim

Chong-man Yun

Jae-gil Lee

Ho-cheol Jang

Kyung-Wook Kim

Tae-hoon Kim

Jong-min Kim

Jin-kyeong Kim

Cheol Choi

A method of fabricating a high-voltage semiconductor device includes the following steps: providing a semiconductor layer; forming a plurality of trenches in the semiconductor layer to define a plurality of pillars of a first conductivity type in the semiconductor layer between adjacent trenches, wherein the trenches extend from a top surface of the semiconductor layer toward a bottom surface of the semiconductor layer; forming a charge compensation layer of a second conductivity type over at least sidewalls of each trench to a predetermined thickness thereby forming a groove in each trench; and substantially filling each groove with a charge compensation plug of the first conductivity type.

Method of fabricating high-voltage semiconductor device

A high-voltage semiconductor device includes a semiconductor layer having a plurality of pillars of a first conductivity type defined by a plurality of trenches which extend from a top surface of the semiconductor layer toward a bottom surface thereof. A charge compensation layer of a second conductivity type is disposed over at least sidewalls of each trench to a predetermined thickness to form a groove in each trench. A charge compensation plug of the first conductivity type substantially fills each groove.

High-voltage semiconductor device and method of fabricating the same

A high voltage semiconductor device including a semiconductor substrate on which a semi-insulating polycrystalline silicon layer is formed to alleviate electric field concentration in a field region, is disclosed. A thermal oxide layer is formed on the semi-insulating polycrystalline silicon layer to serve as a protective layer. The thermal oxide layer forms a good interface with the semi-insulating polycrystalline silicon layer compared to a wet etched oxide layer or a chemical vapor deposition (CVD) oxide layer, thereby decreasing the amount of leakage current. In addition, compared to a dual semi-insulating polycrystalline silicon layer, the thermal oxide layer exhibits a high surface protection effect and a high resistance against dielectric breakdown. It also allows a great reduction in fabrication time. In particular, the semi-insulating polycrystalline silicon layer is removed from the active region, thereby preventing the direct current (DC) gain of a device from being lowered within a low collector current range caused by the semi-insulating polycrystalline silicon layer.

Method of fabricating a high voltage semiconductor device using SIPOS

Growing community of inventors

Gyeonggi-do, South Korea

Chang-wook Kim