Samsung Electronics Co., Ltd.

Chang-wook Jeong

In Huh

Jeong-hoon Ko

Kwang-il Park

Seung-ju Kim

Tae-ho Lee

Youn-sik Park

Hyo-jin Choi

Joon-wan Chai

Young-min Oh

Jun-haeng Lee

Hyun-sun Park

Jae-jun Lee

Dong-won Kim

Keun-Ho Lee

Nak-jin Son

Ui-hui Kwon

Young-Kwan Park

Seong-Je Kim

Seung-Hyun Song

Kwang-Seok Lee

A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.

Device for generating verification vector for circuit design verification, circuit design system, and reinforcement learning method of the device and the circuit design system

A method of selecting a model of machine learning executed by a processor is provided. The method includes: receiving at least one data-set; configuring a configuration space for machine learning of the at least one data-set; extracting, from the at least one data-set, a meta-feature including quantitative information about the data-set; calculating performance of the machine learning for the at least one data-set based on a plurality of configurations included in the configuration space; executing meta-learning based on the meta-feature, the plurality of configurations, and the calculated performance; and optimizing the configuration space based on a result of executing the meta-learning.

Method and apparatus for selecting model of machine learning based on meta-learning

A device for verifying a circuit design including a first circuit block and a second circuit block includes a verification vector generator and a design verifier. The verification vector generator determines a first verification vector by performing reinforcement learning through neural network computation based on a coverage corresponding to a first test vector, the coverage being determined based on a state transition of the first circuit block generated by inputting the first test vector to the first circuit block. The design verifier performs design verification for the first circuit block by using the first verification vector.

Provided are a method for fabricating a semiconductor device The method for fabricating include providing a substrate including a first region and a second region, the first region including first and second sub-regions, and the second region including third and fourth sub-regions, forming first to fourth fins on the first and second regions to protrude from the substrate, the first fin being formed on the first sub-region, the second fin being formed on the second sub-region, the third fin being formed on the third sub-region, and the fourth fin being formed on the fourth sub-region, forming first to fourth dummy gate structures to intersect the first to fourth fins, the first dummy gate structure being formed on the first fin, the second dummy gate structure being formed on the second fin, the third dummy gate structure being formed on the third fin, and the fourth dummy gate structure being formed on the fourth fin, forming a first doped region in each of the first and second fins and a second doped region in each of the third and fourth fins by doping impurities into the first to fourth fins on both sides of the first to fourth dummy gate structures by performing an ion implantation process simultaneously in the first and second regions; and removing the first doped region of the first fin and the second doped region of the third fin, or removing the first doped region of the second fin and the second doped region of the fourth fin.

Method for fabricating semiconductor device

Growing community of inventors

Hwaseong-si, South Korea

Chang-wook Jeong