Samsung Electronics Co., Ltd.

Other

Chang-Woo Oh

Dong-Gun Park

Dong-won Kim

Dong-Won Kim

Jeong-Dong Choe

Sung-young Lee

Sung-Hwan Kim

Kyoung-hwan Yeo

Sung-Min Kim

Ming Li

Min-sang Kim

Eun-jung Yun

Sung-Dae Suk

Yong-Kyu Lee

Dong-Uk Choi

Myung-Gil Kang

Ki-Whan Song

Na-Young Kim

Sung-Bong Kim

Hye-Jin Cho

Byung-yong Choi

Sung-hwan Kim

Yong-lack Choi

Chang-Sub Lee

Yong-kyu Lee

Shin-Ae Lee

Choong-Ho Lee

Woo-Yeong Cho

Chul Ho Lee

Jae-Man Yoon

Nam-Kyun Tak

Young-Chai Jung

An integrated circuit device includes a first transistor having a first channel between a first source/drain, and a second transistor having a second channel between a second source/drain. The first transistor operates based on a first amount of current and the second transistor operates based on a second amount of current different from the first amount of current. The first and second channels have fixed channel widths. The fixed channel widths may be based on fins or nanowires included in the first and second transistors.

Integrated circuit devices

Method of fabricating integrated circuit devices

An integrated circuit can include first and second FETs of a particular conductivity type on a substrate, wherein a first source/drain region of the first FET is closer to a center of a first channel region of the first FET than a second source/drain region of the second FET is to a center of a second channel region of the second FET.

Integrated circuit devices including stress proximity effects and methods of fabricating the same

Integrated circuit devices and fabricating method thereof

Semiconductor devices include a semiconductor substrate with a stack structure protruding from the semiconductor substrate and surrounded by an isolation structure. The stack structure includes an active layer pattern and a gap-filling insulation layer between the semiconductor substrate and the active layer pattern. A gate electrode extends from the isolation structure around the stack structure. The gate electrode is configured to provide a support structure for the active layer pattern. The gate electrode may be a gate electrode of a silicon on insulator (SOI) device formed on the semiconductor wafer and the semiconductor device may further include a bulk silicon device formed on the semiconductor substrate in a region of the semiconductor substrate not including the gap-filing insulation layer.

Methods of manufacturing semiconductor devices having a support structure for an active layer pattern

Provided is a semiconductor device. The semiconductor device includes a semiconductor substrate, a first isolation dielectric pattern on the semiconductor substrate, and an active pattern on the first isolation dielectric pattern. A semiconductor pattern is interposed between the semiconductor substrate and the first isolation dielectric pattern, and a second isolation dielectric pattern is interposed between the semiconductor substrate and the semiconductor pattern. The semiconductor substrate and the semiconductor pattern are electrically connected by a connection pattern.

Semiconductor devices with connection patterns

A field effect transistor includes a buried gate pattern that is electrically isolated by being surrounded by a tunneling insulating film. The field effect transistor also includes a channel region that is floated by source and drain regions, a gate insulating film, and the tunneling insulating film. The buried gate pattern and the tunneling insulating film extend into the source and drain regions. Thus, the field effect transistor efficiently stores charge carriers in the buried gate pattern and the floating channel region.

Field effect transistor with buried gate pattern

A fin field-effect transistor (FinFET) device includes a fin-shaped active region having first and second source/drain regions therein and a channel region therebetween vertically protruding from a semiconductor substrate. A gate electrode is formed on an upper surface and sidewalls of the channel region. First and second source/drain contacts are formed on respective upper surfaces and sidewalls of the first and second source/drain regions of the fin-shaped active region at opposite sides of the gate electrode. The channel region may be narrower than the first and second source/drain regions of the fin-shaped active region.

Vertical channel fin field-effect transistors having increased source/drain contact area and methods for fabricating the same

A semiconductor device may include a substrate, an active semiconductor region of the substrate, and a gate electrode. The active semiconductor region may include a channel region between first and second junction regions. The channel region may include a first semiconductor material, the first and second junction regions may include a second semiconductor material, and the first and second semiconductor materials may be different. The gate electrode may be on the channel region with portions of the first and second junction regions being free of the gate electrode.

Semiconductor devices including fin shaped semiconductor regions and stress inducing layers

Semiconductor devices having a support structure for an active layer pattern

A field effect transistor (FET) and a method for manufacturing the same, in which the FET may include an isolation film formed on a semiconductor substrate to define an active region, and a gate electrode formed on a given portion of the semiconductor substrate. A channel layer may be formed on a portion of the gate electrode, with source and drain regions formed on either side of the channel layer so that boundaries between the channel layer and the source and drain regions of the FET may be perpendicular to a surface of the semiconductor substrate.

Field effect transistor and method for manufacturing the same

Exposed are a semiconductor device and method of fabricating the same. The device includes an insulation film that is disposed between an active pattern and a substrate, which provides various improvements. This structure enhances the efficiency of high integration and offers an advanced structure for semiconductor devices.

Semiconductor devices and methods of fabricating the same

A semiconductor device having a floating body element and a bulk body element and a manufacturing method thereof are provided. The semiconductor device includes a substrate having a bulk body element region and floating body element regions. An isolation region defining an active region of the bulk body element region of the substrate and defining first buried patterns and first active patterns, which are sequentially stacked on a first element region of the floating body element regions of the substrate is provided. A first buried dielectric layer interposed between the first buried patterns and the substrate and between the first buried patterns and the first active patterns is provided.

Semiconductor device having floating body element and bulk body element

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Gyeonggi-do, South Korea

Chang-Woo Oh