Samsung Electronics Co., Ltd.

Chang-Won Choi

Ki-Hyun Hwang

Bon-Young Koo

Jong-Ho Park

Woo-Sik Kim

Seok-woo Nam

Shin-woo Nam

Dae-hyuk Chung

Bum-su Kim

Yeo-cheol Yoon

Ji-hwan Choi

Han-jin Lim

Young-hyun Kim

Chang-won Kim

Jung-Hyun Hwang

Chang-Hwan Lee

Chul Ho Jung

Tae-hoon Lee

Doo-Won Lee

Min-Seok Han

Han-jin Park

No-Hyun Huh

Keun-Bok Kim

Sung-min Lim

Tae-Kyun Kang

Young-in Park

Jung-Bong Yun

Young-Sub Yu

Byeung-Wook Choi

Doo-Whan Choi

Han-Ul Moon

Chul-Kyun Seok

Disclosed is an electronic device. The electronic device of the present invention comprises: a communication unit; a storage unit for storing a uniform resource locator (URL) designated by an external electronic device and information on specific content provided in the designated URL; and a processor which, when a request for a connection to a designated URL is received from an external electronic device through the communication unit, identifies whether specific content can be provided in the designated URL, and in a case where the specific content cannot be provided, obtains information on another URL that provides content related to the specific content by using stored information, and transmits the obtained information on the another URL to the external electronic device through the communication unit.

Electronic device and control method therefor

A method of forming a coating layer, including preparing hollow inorganic particles, each hollow inorganic particle including a shell surrounding a hollow core; preparing inorganic coating particles of a solid structure; forming a mixture of the hollow inorganic particles and the inorganic coating particles; and spraying the mixture on a surface of a base by a plasma spray coating process.

Methods of forming coating layers

A method of forming a transistor is provided. An upper portion of a substrate is partially removed forming a trench. An isolation layer partially fills the trench, forming active patterns of the substrate. The isolation layer has a void therein. A photoresist pattern is formed on the active patterns and the isolation layer. The active patterns and the isolation layer are partially removed using the photoresist pattern as an etching mask, thus forming a recess. A plasma treatment process is performed, removing the photoresist pattern and filling the void. A gate insulation layer and a gate electrode fill the recess.

Methods of forming transistors and methods of manufacturing semiconductor devices including the transistors

A method for transmitting Ethernet data in a Digital Unit (DU) that processes a baseband and interfaces with at least two Radio Frequency (RF) Units (RUs) is provided. The method includes setting location information of two or more Ethernet channels in a first subchannel of a radio frame, allocating the two or more Ethernet channels in second subchannels of the radio frame, using the location information, and transmitting the radio frame to the at least two RUs.

Method for transmitting and receiving ethernet data between digital unit and RF unit and apparatus thereof

Methods of forming integrated circuit capacitors include the steps of forming a first electrically insulating layer having a conductive plug therein, on a semiconductor substrate, and then forming second and third electrically insulating layers of different materials on the first electrically insulating layer. A contact hole is then formed to extend through the second and third electrically insulating layers and expose the conductive plug. Next, a conductive layer is formed in the contact hole and on the third electrically insulating layer. A step is then performed to planarize the conductive layer to define a U-shaped electrode in the contact hole. The third electrically insulating layer is then etched-back to expose upper portions of outer sidewalls of the U-shaped electrode, using the second electrically insulating layer as an etch stop layer. However, the second electrically insulating layer is not removed but is left to act as a supporting layer for the U-shaped electrode. This second electrically insulating layer preferably comprises a composite of a nitride layer and an oxide layer. To increase the effective surface area of the U-shaped electrode, an HSG layer may also be formed on the inner and outer sidewalls of the U-shaped electrode.

Dram cell capacitors having U-shaped electrodes with rough inner and outer surfaces

An end point detection window prevents process failures in a plasma etching device. The end point detection window has a body of aluminum or an aluminum alloy through which a hole extends to provide a path along which light generated during the etching process can pass from the process chamber, and a capping section coupled to a light outlet of the body. The capping section is of quartz for allowing the light passing through the hole in the body to be transmitted out of the process chamber.

Window for allowing end point of etching process to be detected and etching device comprising the same

A semiconductor device having a chamfered silicide layer and a manufacturing method of the same. The semiconductor device includes: a first insulation layer overlying a semiconductor substrate; gate structures including first conductive layer patterns formed on the first insulation layer, and second conductive layer patterns which are formed on the first conductive layer patterns, wherein the lower sides of the second conductive layer patterns are substantially perpendicular to the major surface of the semiconductor substrate and the upper sides of the second conductive layer patterns are chamfered; and a second insulation layer formed with a first width W on the second conductive layer patterns, wherein the sidewalls of the second insulation layer overhang the upper edges of the second conductive layer patterns. In the semiconductor device manufacture, in forming undercut regions which define the chamfered upper edges of the metal silicide layer patterns, isotropic dry etching is carried out, wherein the isotropic dry etching can be performed simultaneously with ashing of photoresist patterns, or immediately after the ashing process in the same chamber. In either case, after the ashing of the photoresist patterns, an isotropic wet etching can be carried out immediately after performing an existing stripping process, so as to form the undercut regions.

Methods of manufacturing semiconductor devices having chamfered silicide layers therein

Semiconductor device having chamfered silicide layer and method for manufacturing the same

Methods of forming integrated circuit capacitors having U-shaped electrodes

Disclosed is an improved method for fabricating a DRAM cell capacitor which can prevent over-etching of polysilicon storage node. The method includes the steps of etching a first insulating layer on a semiconductor substrate to form a storage contact hole, filling the storage contact hole with a first conductive material to form a storage contact plug, forming a second insulating layer over the first insulating layer including the storage contact plug, forming a mask over the second insulating layer to define a storage node region, using the mask and etching the second and first insulating layers to form an opening therein to an upper surface of the storage contact plug, and filling the opening with a second conductive material to form a storage node.

Method for fabricating a DRAM cell capacitor including forming first

Growing community of inventors

Seoul, South Korea

Chang-Won Choi