Samsung Electronics Co., Ltd.

Postech Academy-industry Foundation

Seoul National University

Chang-Su Kim

Han-Gu Kim

Young-Min Kim

Jong-Won Lee

Young-Lim Park

Jin-il Lee

Soon-Oh Park

Gyu-Hwan Oh

Kyoung-sei Choi

Sang-Uk Lee

In-Kyu Park

Shin-Jun Lee

Kyoung-Ki Jeon

Kyong-Soon Cho

Jae-Hyok Ko

Kwan-Jai Lee

Keung-beum Kim

Han-Jun Kim

Min-Chang Ko

Han-gu Kim

Jae-hyok Ko

Sung-Pil Jang

Jong-Hee Yoon

Jun-Mo Park

Sung-Jun Song

Seon-Yeong Heo

Hye-Yeon Chung

Moon-Seok Yang

An electrostatic discharge (ESD) protection circuit is provided. The ESD protection circuit includes a transient-state detection circuit configured to generate a dynamic triggering signal based on a voltage change rate of a voltage on a first power rail; a voltage detection circuit configured to generate a static triggering signal based on the voltage on the first power rail; a trigger circuit configured to generate a discharge control signal based on the dynamic triggering signal and the static triggering signal; and a main discharge circuit configured to discharge an electric charge from the first power rail to a second power rail based on the discharge control signal.

Electrostatic discharge (ESD) protection circuit and integrated circuit including the same

In a method of compiling an updated program having a plurality of updated functions that is updated from an original program having a plurality of original functions, it is determined whether a first original function corresponding to a first updated function exists, it is determined whether the first updated function is changed from the first original function, a first optimization combination for the first updated function is searched when the first original function does not exist or when the first updated function is changed from the first original function, a second optimization combination applied to the first original function is read from a configuration database storing optimization combinations for the original functions when the first original function exists and the first updated function is not changed from the first original function, and the updated program is compiled using the first optimization combination or the second optimization combination.

Method of compiling a program

A film-type semiconductor package includes a semiconductor integrated circuit and a dummy metal pattern. The semiconductor integrated circuit is formed on a film and includes an electrostatic discharge (ESD) protection circuit. The dummy metal pattern is formed on the film and is electrically connected to the ESD protection circuit through a first wiring formed on the film.

Film-type semiconductor packages and display devices having the same

A method of manufacturing a diode is provided. An N-type well region is formed in a first upper portion of an N-type epitaxial layer. A P-type drift region is formed in a second upper portion of the N-type epitaxial layer. An N-type doping region is formed in the N-type well region. A P-type doping region is formed in the P-type drift region. An isolation structure is formed in the P-type drift region. The isolation structure is disposed between the P-type doping region and the N-type well region. A first electrode is formed on a portion of the N-type epitaxial layer. The portion of the N-type epitaxial layer is disposed between the N-type well region and the P-type drift region. The first electrode overlaps a portion of the isolation structure. A connection structure is formed to electrically couple the N-type doping region and the first electrode.

Diode, ESD protection circuit and method of manufacturing the same

A structure of a semiconductor chip package is provided. The semiconductor chip package includes: a substrate; a semiconductor chip mounted on a first surface of the substrate; a plurality of electrode pads on a second surface, different from the first surface, of the substrate; and an electrostatic discharge protection pad overlapping a portion of a first electrode pad and a portion of a second electrode pad among the plurality of electrode pads.

Semiconductor chip package

Provided is a method of fabricating a phase-change memory device. The phase-change memory device includes a memory cell having a switching device and a phase change pattern. The method includes; forming a TiC layer on a contact electrically connecting the switching device using a plasma enhanced cyclic chemical vapor deposition (PE-cyclic CVD) process, patterning the TiC layer to form a lower electrode on the contact, and forming the phase-change pattern on the lower electrode.

Method of fabricating phase-change memory device having TiC layer

Growing community of inventors

Hwaseong-si, South Korea

Chang-Su Kim